公开(公告)号：US08716818B2

公开(公告)日：2014-05-06

申请号：US13428465

申请日：2012-03-23

申请人： Masatoshi Yoshikawa ,  Satoshi Seto ,  Hideaki Harakawa ,  Jyunichi Ozeki ,  Tatsuya Kishi ,  Keiji Hosotani

发明人： Masatoshi Yoshikawa ,  Satoshi Seto ,  Hideaki Harakawa ,  Jyunichi Ozeki ,  Tatsuya Kishi ,  Keiji Hosotani

IPC分类号： H01L29/82 ,  G11C11/02

CPC分类号： H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： According to one embodiment, a magnetoresistive element includes a storage layer having a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on sidewalls of the reference layer and the hard mask layer. An in-plane size of the reference layer is smaller than an in-plane size of the storage layer. A difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less. The sidewall spacer layer includes a material selected from a group of a diamond, DLC, BN, SiC, B4C, Al2O3 and AlN.

摘要翻译： 根据一个实施例，磁阻元件包括具有可变和垂直磁化的存储层，存储层上的隧道势垒层，在隧道势垒层上具有不变和垂直磁化的参考层，参考上的硬掩模层 层和在参考层和硬掩模层的侧壁上的侧壁间隔层。 参考层的面内尺寸小于存储层的面内尺寸。 存储层和参考层的面内尺寸之差为2nm以下。 侧壁间隔层包括选自金刚石，DLC，BN，SiC，B4C，Al2O3和AlN的材料。

公开(公告)号：US20130001652A1

公开(公告)日：2013-01-03

申请号：US13428465

申请日：2012-03-23

申请人： Masatoshi Yoshikawa ,  Satoshi Seto ,  Hideaki Harakawa ,  Jyunichi Ozeki ,  Tatsuya Kishi ,  Keiji Hosotani

发明人： Masatoshi Yoshikawa ,  Satoshi Seto ,  Hideaki Harakawa ,  Jyunichi Ozeki ,  Tatsuya Kishi ,  Keiji Hosotani

IPC分类号： H01L29/82 ,  H01L21/02

CPC分类号： H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： According to one embodiment, a magnetoresistive element includes a storage layer having a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on sidewalls of the reference layer and the hard mask layer. An in-plane size of the reference layer is smaller than an in-plane size of the storage layer. A difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less. The sidewall spacer layer includes a material selected from a group of a diamond, DLC, BN, SiC, B4C, Al2O3 and AlN.

摘要翻译： 根据一个实施例，磁阻元件包括具有可变和垂直磁化的存储层，存储层上的隧道势垒层，在隧道势垒层上具有不变和垂直磁化的参考层，参考上的硬掩模层 层和在参考层和硬掩模层的侧壁上的侧壁间隔层。 参考层的面内尺寸小于存储层的面内尺寸。 存储层和参考层的面内尺寸之差为2nm以下。 侧壁间隔层包括选自金刚石，DLC，BN，SiC，B4C，Al2O3和AlN的材料。

公开(公告)号：US09035402B2

公开(公告)日：2015-05-19

申请号：US13963710

申请日：2013-08-09

申请人： Yoshiaki Asao ,  Hideaki Harakawa

发明人： Yoshiaki Asao ,  Hideaki Harakawa

IPC分类号： H01L43/08 ,  H01L27/22 ,  G11C11/16

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1675 ,  H01L43/08

摘要： According to one embodiment, a semiconductor memory device comprises a cell transistor includes a first gate electrode buried in a semiconductor substrate and a first diffusion layer and a second diffusion layer formed to sandwich the first gate electrode, a first lower electrode formed on the first diffusion layer, a magnetoresistive element formed on the first lower electrode to store data according to a change in a magnetization state and connected to a bit line located above, a second lower electrode formed on the second diffusion layer, and a first contact formed on the second lower electrode and connected to a source line located above. A contact area between the second lower electrode and the second diffusion layer is larger than a contact area between the first contact and the second lower electrode.

摘要翻译： 根据一个实施例，一种半导体存储器件包括：单元晶体管，包括埋在半导体衬底中的第一栅电极和形成为夹着第一栅电极的第一扩散层和第二扩散层;形成在第一扩散层上的第一下电极 层，形成在所述第一下电极上以根据磁化状态的变化存储数据并连接到位于上方的位线的磁阻元件，形成在所述第二扩散层上的第二下电极，以及形成在所述第二扩散层上的第一触点 下电极并连接到位于上方的源极线。 第二下部电极和第二扩散层之间的接触面积大于第一接触部和第二下部电极的接触面积。

公开(公告)号：US08232197B2

公开(公告)日：2012-07-31

申请号：US12585238

申请日：2009-09-09

申请人： Makoto Honda ,  Kaori Yomogihara ,  Kazuhiro Murakami ,  Masanori Numano ,  Takahito Nagamatsu ,  Hideaki Harakawa ,  Hideto Matsuyama ,  Hirokazu Ezawa ,  Hisashi Kaneko

发明人： Makoto Honda ,  Kaori Yomogihara ,  Kazuhiro Murakami ,  Masanori Numano ,  Takahito Nagamatsu ,  Hideaki Harakawa ,  Hideto Matsuyama ,  Hirokazu Ezawa ,  Hisashi Kaneko

IPC分类号： H01L21/4763 ,  H01L21/28

CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76814

摘要： An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.

摘要翻译： 对形成在导电层上的绝缘膜进行干蚀刻，以在绝缘膜上形成连接孔，使导电层露出。 将等离子体供应到暴露的导电层上以干燥在连接孔中产生的损伤层。 作为干式清洗的连接孔中产生的产品通过湿法除去。 通过使用包括NF 3或HF的气体的化学干法，蚀刻形成在连接孔中的作为湿法处理的结果的氧化膜。 通过热处理除去作为蚀刻结果产生的可热分解的反应产物。

公开(公告)号：US08053268B2

公开(公告)日：2011-11-08

申请号：US12259732

申请日：2008-10-28

申请人： Mari Otsuka ,  Hiroyuki Kamijiyo ,  Hideaki Harakawa

发明人： Mari Otsuka ,  Hiroyuki Kamijiyo ,  Hideaki Harakawa

IPC分类号： H01L21/00

CPC分类号： H01L27/14625 ,  H01L27/14636 ,  H01L27/14685

摘要： A semiconductor device has a semiconductor substrate including a light receiving element, a silicon oxide film formed on the semiconductor substrate, a plurality of wiring interlayer films formed on the silicon oxide film, and each including a wiring layer formed as the result of the fact that copper is buried, and a silicon nitride film formed on the wiring interlayer film of the uppermost layer wherein Si—H concentration is smaller than N—H concentration.

摘要翻译： 半导体器件具有包括光接收元件的半导体衬底，形成在半导体衬底上的氧化硅膜，形成在氧化硅膜上的多个布线层间膜，并且每个包括布线层，其结果是， 铜被埋置，并且在最上层的布线层间膜上形成氮化硅膜，其中Si-H浓度小于N-H浓度。

公开(公告)号：US20100003816A1

公开(公告)日：2010-01-07

申请号：US12585238

申请日：2009-09-09

申请人： Makoto Honda ,  Kaori Yomogihara ,  Kazuhiro Murakami ,  Masanori Numano ,  Takahito Nagamatsu ,  Hideaki Harakawa ,  Hideto Matsuyama ,  Hirokazu Ezawa ,  Hisashi Kaneko

发明人： Makoto Honda ,  Kaori Yomogihara ,  Kazuhiro Murakami ,  Masanori Numano ,  Takahito Nagamatsu ,  Hideaki Harakawa ,  Hideto Matsuyama ,  Hirokazu Ezawa ,  Hisashi Kaneko

IPC分类号： H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76814

摘要： An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.

摘要翻译： 对形成在导电层上的绝缘膜进行干蚀刻，以在绝缘膜上形成连接孔，使导电层露出。 将等离子体供应到暴露的导电层上以干燥在连接孔中产生的损伤层。 作为干式清洗的连接孔中产生的产品通过湿法除去。 通过使用包括NF 3或HF的气体的化学干法，蚀刻形成在连接孔中的作为湿法处理的结果的氧化膜。 通过热处理除去作为蚀刻结果产生的可热分解的反应产物。

公开(公告)号：US20080197398A1

公开(公告)日：2008-08-21

申请号：US12031297

申请日：2008-02-14

申请人： Toshiaki KOMUKAI ,  Hideaki Harakawa

发明人： Toshiaki KOMUKAI ,  Hideaki Harakawa

IPC分类号： H01L29/94 ,  H01L21/8242

CPC分类号： H01L27/0629 ,  H01L28/60 ,  H01L29/7833

摘要： A semiconductor device according to an embodiment of the present invention includes: a transistor including, a gate insulator formed of an insulating layer deposited on a substrate, and a gate electrode formed of an electrode layer deposited on the insulating layer; a capacitor including, a first capacitor electrode formed of the electrode layer, a first capacitor insulator formed on the first capacitor electrode, a second capacitor electrode formed on the first capacitor insulator, a second capacitor insulator formed on the second capacitor electrode, and a third capacitor electrode formed on the second capacitor insulator; and line patterns which are in contact with a contact plug for the transistor, a contact plug for the first capacitor electrode, a contact plug for the second capacitor electrode, and the third capacitor electrode.

摘要翻译： 根据本发明实施例的半导体器件包括：晶体管，包括由沉积在衬底上的绝缘层形成的栅极绝缘体和由沉积在绝缘层上的电极层形成的栅电极; 电容器，包括由电极层形成的第一电容器电极，形成在第一电容器电极上的第一电容器绝缘体，形成在第一电容器绝缘体上的第二电容器电极，形成在第二电容器电极上的第二电容器绝缘体，以及第三电容器绝缘体 电容器电极形成在第二电容绝缘体上; 以及与晶体管的接触插塞接触的线路图案，第一电容器电极的接触插头，第二电容器电极的接触插塞和第三电容器电极。

公开(公告)号：US20050191817A1

公开(公告)日：2005-09-01

申请号：US11066227

申请日：2005-02-25

申请人： Toshiaki Komukai ,  Hideaki Harakawa

发明人： Toshiaki Komukai ,  Hideaki Harakawa

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： According to an aspect of the invention, there is provided a semiconductor device comprising a semiconductor substrate, a gate electrode formed on the substrate via a gate insulating film and containing silicon, an insulating offset spacer formed on a side surface of the gate electrode and having an upper surface lower than an upper surface of the gate electrode, an insulating sidewall spacer formed on an upper side surface of the gate electrode and on a side surface of the offset spacer by using a material different from the offset spacer, a lightly doped impurity diffusion layer formed in the semiconductor substrate so as to sandwich the gate electrode, a heavily doped impurity diffusion layer formed in the semiconductor substrate in a position deeper than the lightly doped impurity diffusion layer, so as to sandwich the gate electrode and sidewall spacer, and a silicide film formed on the gate electrode.

摘要翻译： 根据本发明的一个方面，提供了一种半导体器件，其包括半导体衬底，通过栅极绝缘膜形成在衬底上并含有硅的栅电极，形成在栅电极的侧表面上的绝缘偏移间隔物，并且具有 通过使用与偏移间隔物不同的材料，形成在栅电极的上侧表面上且在偏置间隔物的侧表面上的绝缘侧壁间隔物，轻掺杂杂质 扩散层，形成在半导体衬底中以将栅电极夹在中间，形成在半导体衬底中的比掺杂稀土杂质扩散层更深的位置的重掺杂杂质扩散层，以夹持栅电极和侧壁间隔，以及 形成在栅电极上的硅化物膜。

公开(公告)号：US07858465B2

公开(公告)日：2010-12-28

申请号：US12031297

申请日：2008-02-14

申请人： Toshiaki Komukai ,  Hideaki Harakawa

发明人： Toshiaki Komukai ,  Hideaki Harakawa

IPC分类号： H01L21/8238

CPC分类号： H01L27/0629 ,  H01L28/60 ,  H01L29/7833

摘要： A semiconductor device according to an embodiment of the present invention includes: a transistor including, a gate insulator formed of an insulating layer deposited on a substrate, and a gate electrode formed of an electrode layer deposited on the insulating layer; a capacitor including, a first capacitor electrode formed of the electrode layer, a first capacitor insulator formed on the first capacitor electrode, a second capacitor electrode formed on the first capacitor insulator, a second capacitor insulator formed on the second capacitor electrode, and a third capacitor electrode formed on the second capacitor insulator; and line patterns which are in contact with a contact plug for the transistor, a contact plug for the first capacitor electrode, a contact plug for the second capacitor electrode, and the third capacitor electrode.

摘要翻译： 根据本发明实施例的半导体器件包括：晶体管，包括由沉积在衬底上的绝缘层形成的栅极绝缘体和由沉积在绝缘层上的电极层形成的栅电极; 电容器，包括由电极层形成的第一电容器电极，形成在第一电容器电极上的第一电容器绝缘体，形成在第一电容器绝缘体上的第二电容器电极，形成在第二电容器电极上的第二电容器绝缘体，以及第三电容器绝缘体 电容器电极形成在第二电容绝缘体上; 以及与晶体管的接触插塞接触的线路图案，第一电容器电极的接触插头，第二电容器电极的接触插塞和第三电容器电极。

公开(公告)号：US07605076B2

公开(公告)日：2009-10-20

申请号：US11346236

申请日：2006-02-03

申请人： Makoto Honda ,  Kaori Yomogihara ,  Kazuhiro Murakami ,  Masanori Numano ,  Takahito Nagamatsu ,  Hideaki Harakawa ,  Hideto Matsuyama ,  Hirokazu Ezawa ,  Hisashi Kaneko

发明人： Makoto Honda ,  Kaori Yomogihara ,  Kazuhiro Murakami ,  Masanori Numano ,  Takahito Nagamatsu ,  Hideaki Harakawa ,  Hideto Matsuyama ,  Hirokazu Ezawa ,  Hisashi Kaneko

IPC分类号： H01L21/4763 ,  H01L21/28 ,  H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76814

摘要： An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.

摘要翻译： 对形成在导电层上的绝缘膜进行干蚀刻，以在绝缘膜上形成连接孔，使导电层露出。 将等离子体供应到暴露的导电层上以干燥在连接孔中产生的损伤层。 作为干式清洗的连接孔中产生的产品通过湿法除去。 通过使用包括NF 3或HF的气体的化学干法，蚀刻形成在连接孔中的作为湿法处理的结果的氧化膜。 通过热处理除去作为蚀刻结果产生的可热分解的反应产物。