公开(公告)号：US20110006557A1

公开(公告)日：2011-01-13

申请号：US12920213

申请日：2009-05-08

申请人： Masayuki Koizumi ,  Yusaku Furukawa

发明人： Masayuki Koizumi ,  Yusaku Furukawa

IPC分类号： B60R7/04

CPC分类号： B60R7/04 ,  B60K2350/925 ,  B60K2350/943 ,  B60R13/0256 ,  B60R13/0262 ,  B60R2013/0293

摘要： A mounting structure for vehicle interior parts includes a console member and a shift panel having an upper panel and a lower panel. An insertion portion that is inserted into a dent formed in a rear end of the console member is provided on a rear end of the lower panel. Left and right outer side surfaces of the insertion portion of the lower panel and left and right inner side surfaces of the dent of the console member are configured to be engageable by inserting engaging projections into engaging recesses. The engaging recesses are provided so as to restrict movements of the engaging projections in their longitudinal direction, and to allow positional deviation of the engaging projections in the vertical direction.

摘要翻译： 用于车辆内部部件的安装结构包括控制台部件和具有上板和下板的换挡板。 插入到形成在控制台构件的后端的凹部中的插入部设置在下板的后端。 下侧板的插入部的左外侧面和右外侧面以及控制台部件的凹部的左右内侧面构成为能够通过将卡定突起插入到卡合凹部中而卡合。 接合凹部被设置成限制接合突起在其纵向方向上的移动，并且允许接合突起在垂直方向上的位置偏移。

公开(公告)号：US08075034B2

公开(公告)日：2011-12-13

申请号：US12920213

申请日：2009-05-08

申请人： Masayuki Koizumi ,  Yusaku Furukawa

发明人： Masayuki Koizumi ,  Yusaku Furukawa

IPC分类号： B60R7/04

CPC分类号： B60R7/04 ,  B60K2350/925 ,  B60K2350/943 ,  B60R13/0256 ,  B60R13/0262 ,  B60R2013/0293

摘要： A mounting structure for vehicle interior parts includes a console member and a shift panel having an upper panel and a lower panel. An insertion portion that is inserted into a dent formed in a rear end of the console member is provided on a rear end of the lower panel. Left and right outer side surfaces of the insertion portion of the lower panel and left and right inner side surfaces of the dent of the console member are configured to be engageable by inserting engaging projections into engaging recesses. The engaging recesses are provided so as to restrict movements of the engaging projections in their longitudinal direction, and to allow positional deviation of the engaging projections in the vertical direction.

摘要翻译： 用于车辆内部部件的安装结构包括控制台部件和具有上板和下板的换挡板。 插入到形成在控制台构件的后端的凹部中的插入部设置在下板的后端。 下侧板的插入部的左外侧面和右外侧面以及控制台部件的凹部的左右内侧面构成为能够通过将卡定突起插入到卡合凹部中而卡合。 接合凹部被设置成限制接合突起在其纵向方向上的移动，并且允许接合突起在垂直方向上的位置偏移。

公开(公告)号：US07468625B2

公开(公告)日：2008-12-23

申请号：US11773996

申请日：2007-07-06

申请人： Masayuki Koizumi ,  Hiroyuki Shibayama

发明人： Masayuki Koizumi ,  Hiroyuki Shibayama

IPC分类号： G05F1/10

CPC分类号： G05F3/262

摘要： A semiconductor device including a plurality of current mirror circuits is disclosed. The current mirror circuits having reference input terminals and output terminals respectively. Each of the reference input terminals is provided with a current having a different current value. Each of the output terminals of the current mirror circuits are connected to a current output terminal. The output currents of the current mirror circuits are controlled by a control circuit.

摘要翻译： 公开了一种包括多个电流镜电路的半导体器件。 电流镜电路分别具有参考输入端和输出端。 每个参考输入端子具有不同电流值的电流。 电流镜电路的每个输出端连接到电流输出端。 电流镜电路的输出电流由控制电路控制。

公开(公告)号：US07088161B2

公开(公告)日：2006-08-08

申请号：US10948349

申请日：2004-09-23

申请人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

发明人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

IPC分类号： H03K3/356

CPC分类号： H03K19/0016

摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

公开(公告)号：US07248100B2

公开(公告)日：2007-07-24

申请号：US11171316

申请日：2005-07-01

申请人： Masayuki Koizumi ,  Hiroyuki Shibayama

发明人： Masayuki Koizumi ,  Hiroyuki Shibayama

IPC分类号： G05F1/10

CPC分类号： G05F3/262

摘要： A semiconductor device including a plurality of current mirror circuits is disclosed. The current mirror circuits having reference input terminals and output terminals respectively. Each of the reference input terminals is provided with a current having a different current value. Each of the output terminals of the current mirror circuits are connected to a current output terminal. The output currents of the current mirror circuits are controlled by a control circuit.

摘要翻译： 公开了一种包括多个电流镜电路的半导体器件。 电流镜电路分别具有参考输入端和输出端。 每个参考输入端子具有不同电流值的电流。 电流镜电路的每个输出端连接到电流输出端。 电流镜电路的输出电流由控制电路控制。

公开(公告)号：US06466503B2

公开(公告)日：2002-10-15

申请号：US09949652

申请日：2001-09-12

申请人： Masayuki Koizumi ,  Hiroyuki Shibayama

发明人： Masayuki Koizumi ,  Hiroyuki Shibayama

IPC分类号： G11C706

CPC分类号： G11C17/12

摘要： A semiconductor memory has paired first and second bit lines one of which passes a current representing data stored in a selected memory cell. If the first bit line transfers the current representing the data stored in the memory cell, the second bit line transfers a current representing data stored in a dummy cell. If the second bit line transfers the current representing the data stored in the memory cell, the first bit line transfers the current representing the data stored in the dummy cell. The current transferred through the first bit line is divided into partial currents, and the current transferred through the second bit line is also divided into partial currents. It is determined whether or not the current representing the data stored in the memory cell is passed through the first bit line. If it is determined that the first bit line passes the current representing the data stored in the memory cell, the partial currents from the first bit line are recombined to provide an output and one of the partial currents from the second bit line is selected to provide another output. If it is determined that the first bit line does not pass the current representing the data stored in the memory cell, i.e., the first bit line passes the current representing the data stored in the dummy cell, the partial currents from the second bit line are recombined to provide an output and one of the partial currents from the first bit line is selected to provide another output.

摘要翻译： 半导体存储器配对第一和第二位线，其中一个通过表示存储在所选存储单元中的数据的电流。 如果第一位线传送表示存储在存储单元中的数据的电流，则第二位线传送表示存储在虚拟单元中的数据的电流。 如果第二位线传送表示存储在存储单元中的数据的电流，则第一位线传送表示存储在虚拟单元中的数据的电流。 通过第一位线传输的电流被分成部分电流，并且通过第二位线传输的电流也被分为部分电流。 确定表示存储在存储单元中的数据的电流是否通过第一位线。 如果确定第一位线通过表示存储在存储单元中的数据的电流，则来自第一位线的部分电流被重组以提供输出，并且选择来自第二位线的部分电流中的一个以提供 另一个输出。 如果确定第一位线未通过表示存储在存储单元中的数据的电流，即，第一位线通过表示存储在虚拟单元中的数据的电流，则来自第二位线的部分电流为 重新组合以提供输出，并且选择来自第一位线的部分电流中的一个以提供另一输出。

公开(公告)号：US5296757A

公开(公告)日：1994-03-22

申请号：US998922

申请日：1992-12-30

申请人： Masayuki Koizumi

发明人： Masayuki Koizumi

IPC分类号： H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/094

CPC分类号： H03K19/00361 ,  H03K19/09429

摘要： The present invention discloses an output circuit which comprises an input terminal for receiving an input signal having a predetermined logic level, an output terminal held at a potential corresponding to the logic level of the input signal, first and second power sources, separated from each other, third and fourth power sources, separated from each other, a fast potential changing circuit, which is connected between the first and third power sources, for instantaneously changing the potential at said output terminal when a logic level of the input signal changes, potential maintaining circuit connected between said second and fourth power sources, for maintaining the potential of the output terminal at the same level after the potential is changed by the rapid potential changing circuit, a first controlling circuit for controlling the fast potential changing circuit such that the fast potential changing circuit starts operating when the logic level of the input signal changes and stops operating after a predetermined time of period elapses, and a second controlling circuit for controlling the potential maintaining circuit such that the potential maintaining circuit starts operating after the fast potential changing circuit starts operating.

摘要翻译： 本发明公开了一种输出电路，包括：输入端子，用于接收具有预定逻辑电平的输入信号;输出端子保持在与输入信号的逻辑电平对应的电位;第一和第二电源彼此分离 第三和第四电源彼此分开，一个连接在第一和第三电源之间的快速电位改变电路，用于当输入信号的逻辑电平改变时瞬时改变所述输出端的电位，电位维持 连接在所述第二和第四电源之间的电路，用于在通过快速电位改变电路改变电位之后将输出端子的电位保持在相同电平;第一控制电路，用于控制快速电位改变电路，使得快速电位 当输入信号的逻辑电平变化时，变化电路开始工作 操作在经过预定时间段之后操作;以及第二控制电路，用于控制电位维持电路，使得在快速电位改变电路开始工作之后电位保持电路开始工作。

公开(公告)号：US07391263B2

公开(公告)日：2008-06-24

申请号：US11511333

申请日：2006-08-29

申请人： Masayuki Koizumi ,  Hiroyuki Shibayama

发明人： Masayuki Koizumi ,  Hiroyuki Shibayama

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F2200/453 ,  H03F2200/78 ,  H03F2203/45366 ,  H03F2203/45454 ,  H03F2203/45466 ,  H03F2203/45484 ,  H03F2203/45702

摘要： An operational amplifier 1 is provided with differential amplifier 2, replica amplifier 3, voltage-current converting circuit 4, reference current source 5 and comparator 6. Differential amplifier 2 includes P-channel MOS transistors PT1 and PT2, gate and drain electrodes of which are connected to each other to function as loads, and N-channel MOS transistors NT1, NT2 and NT3. Replica amplifier 3 is identical in structure to differential amplifier and also includes P-channel MOS transistors PT11 and PT12, gate and drain electrodes of which are connected to each other to function as loads, and N-channel MOS transistors NT11, NT12 and NT13. Voltage-current converting circuit 4 converts output voltages of replica amplifier 3 to current Irep. Comparator 6 compares output current Irep of voltage-current converting circuit 4 with reference current Iref of reference current source 5 and supplies compared current Ico to differential amplifier 2 to keep bias current Ibias of differential amplifier 2 constant.

摘要翻译： 运算放大器1设置有差分放大器2，复制放大器3，电压电流转换电路4，参考电流源5和比较器6。 差分放大器2包括P沟道MOS晶体管PT 1和PT 2，栅极和漏极彼此连接起来用作负载，N沟道MOS晶体管NT1，NT2和NT3。 复制放大器3在结构上与差分放大器相同，并且还包括P沟道MOS晶体管PT 11和PT 12，栅极和漏极彼此连接以用作负载，并且N沟道MOS晶体管NT 11，NT 12和NT 13。 电压电流转换电路4将复制放大器3的输出电压转换为电流Irep。 比较器6将电压 - 电流转换电路4的输出电流Irep与参考电流源5的参考电流Iref进行比较，并将比较电流Ico提供给差分放大器2，以保持差分放大器2的偏置电流Ibias恒定。

公开(公告)号：US20070057724A1

公开(公告)日：2007-03-15

申请号：US11511333

申请日：2006-08-29

申请人： Masayuki Koizumi ,  Hiroyuki Shibayama

发明人： Masayuki Koizumi ,  Hiroyuki Shibayama

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F2200/453 ,  H03F2200/78 ,  H03F2203/45366 ,  H03F2203/45454 ,  H03F2203/45466 ,  H03F2203/45484 ,  H03F2203/45702

摘要： An operational amplifier 1 is provided with differential amplifier 2, replica amplifier 3, voltage-current converting circuit 4, reference current source 5 and comparator 6. Differential amplifier 2 includes P-channel MOS transistors PT1 and PT2, gate and drain electrodes of which are connected to each other to function as loads, and N-channel MOS transistors NT1, NT2 and NT3. Replica amplifier 3 is identical in structure to differential amplifier and also includes P-channel MOS transistors PT11 and PT12, gate and drain electrodes of which are connected to each other to function as loads, and N-channel MOS transistors NT11, NT12 and NT13. Voltage-current converting circuit 4 converts output voltages of replica amplifier 3 to current Irep. Comparator 6 compares output current Irep of voltage-current converting circuit 4 with reference current Iref of reference current source 5 and supplies compared current Ico to differential amplifier 2 to keep bias current Ibias of differential amplifier 2 constant.

摘要翻译： 运算放大器1设置有差分放大器2，复制放大器3，电压电流转换电路4，参考电流源5和比较器6。 差分放大器2包括P沟道MOS晶体管PT 1和PT 2，栅极和漏极彼此连接起来用作负载，N沟道MOS晶体管NT1，NT2和NT3。 复制放大器3在结构上与差分放大器相同，并且还包括P沟道MOS晶体管PT 11和PT 12，栅极和漏极彼此连接以用作负载，并且N沟道MOS晶体管NT 11，NT 12和NT 13。 电压电流转换电路4将复制放大器3的输出电压转换为电流Irep。 比较器6将电压 - 电流转换电路4的输出电流Irep与参考电流源5的参考电流Iref进行比较，并将比较电流Ico提供给差分放大器2，以保持差分放大器2的偏置电流Ibias恒定。

公开(公告)号：US20050035802A1

公开(公告)日：2005-02-17

申请号：US10946398

申请日：2004-09-21

申请人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

发明人： Toshiyuki Furusawa ,  Daisuke Sonoda ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masayuki Koizumi ,  Hidemasa Zama ,  Masahiro Kanazawa

IPC分类号： H01L21/822 ,  H01L27/04 ,  H03K19/00 ,  H03K3/02

CPC分类号： H03K19/0016

摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.