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    Low voltage column decoder sharing a memory array p-well
    5.
    发明授权
    Low voltage column decoder sharing a memory array p-well 有权
    共享一个存储阵列p-well的低压列解码器

    公开(公告)号：US07447071B2

    公开(公告)日：2008-11-04

    申请号：US11557627

    申请日：2006-11-08

    申请人： Massimiliano Frulio ,  Stefano Surico ,  Andrea Sacco ,  Davide Manfre

    发明人： Massimiliano Frulio ,  Stefano Surico ,  Andrea Sacco ,  Davide Manfre

    IPC分类号： G11C11/34

    CPC分类号： G11C16/08

    摘要： A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias the p-well region and a plurality of high-voltage switches are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders. One or more intermediate-level column decoders are formed as low-voltage selector transistors in the p-well between the first-level column decoder and the last-level column decoder. Each of the intermediate-level column decoders also has a high-voltage switch that is activated during a memory erase mode of operation to provide a high voltage to gate terminals of the intermediate-level column decoders.

    摘要翻译： 多个存储器子阵列形成在p阱区域中。 每个存储器子阵列具有至少一个第一级列解码器，其包括也形成在p阱内的多个低压MOS选择晶体管。 最后一级解码器形成在p阱区域外部，并且包括高电压MOS晶体管，以向读出放大器阵列之一提供输出信号。 在存储器擦除操作模式期间，提供高电压以偏置p阱区域，并且激活多个高压开关以向第一级列解码器中的选择器晶体管的栅极端提供高电压。 在第一级列解码器和最后一级列解码器之间的p阱中形成一个或多个中间级列解码器作为低电压选择晶体管。 每个中间级列解码器还具有在存储器擦除操作模式期间激活的高压开关，以向中级列解码器的栅极端提供高电压。

    LOW VOLTAGE COLUMN DECODER SHARING A MEMORY ARRAY P-WELL
    6.
    发明申请
    LOW VOLTAGE COLUMN DECODER SHARING A MEMORY ARRAY P-WELL 有权
    低电压柱解码器共享存储阵列P-WELL

    公开(公告)号：US20080123415A1

    公开(公告)日：2008-05-29

    申请号：US11557627

    申请日：2006-11-08

    申请人： Massimiliano Frulio ,  Stefano Surico ,  Andrea Sacco ,  Davide Manfre

    发明人： Massimiliano Frulio ,  Stefano Surico ,  Andrea Sacco ,  Davide Manfre

    IPC分类号： G11C16/14 ,  G11C16/04

    CPC分类号： G11C16/08

    摘要： A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias the p-well region and a plurality of high-voltage switches are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders. One or more intermediate-level column decoders are formed as low-voltage selector transistors in the p-well between the first-level column decoder and the last-level column decoder. Each of the intermediate-level column decoders also has a high-voltage switch that is activated during a memory erase mode of operation to provide a high voltage to gate terminals of the intermediate-level column decoders.

    摘要翻译： 多个存储器子阵列形成在p阱区域中。 每个存储器子阵列具有至少一个第一级列解码器，其包括也形成在p阱内的多个低压MOS选择晶体管。 最后一级解码器形成在p阱区域外部，并且包括高电压MOS晶体管，以向读出放大器阵列之一提供输出信号。 在存储器擦除操作模式期间，提供高电压以偏置p阱区域，并且激活多个高压开关以向第一级列解码器中的选择器晶体管的栅极端提供高电压。 在第一级列解码器和最后一级列解码器之间的p阱中形成一个或多个中间级列解码器作为低电压选择晶体管。 每个中间级列解码器还具有在存储器擦除操作模式期间激活的高压开关，以向中级列解码器的栅极端提供高电压。

    Sense amplifier with stages to reduce capacitance mismatch in current mirror load
    7.
    发明申请
    Sense amplifier with stages to reduce capacitance mismatch in current mirror load 有权
    具有阶段的感应放大器，以减少电流镜像负载中的电容失配

    公开(公告)号：US20080170454A1

    公开(公告)日：2008-07-17

    申请号：US11652770

    申请日：2007-01-12

    申请人： Gabriele Pelli ,  Lorenzo Bedarida ,  Massimiliano Frulio ,  Davide Manfre

    发明人： Gabriele Pelli ,  Lorenzo Bedarida ,  Massimiliano Frulio ,  Davide Manfre

    IPC分类号： G11C7/06

    CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C16/28 ,  G11C2207/063

    摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.

    摘要翻译： 一种用于读取存储器单元状态的读出放大器电路。 在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。 耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上 不受由第一和第二级的瞬态特性提供的电容电流分量的影响。

    Sense amplifier with stages to reduce capacitance mismatch in current mirror load
    8.
    发明授权
    Sense amplifier with stages to reduce capacitance mismatch in current mirror load 有权
    具有阶段的感应放大器，以减少电流镜像负载中的电容失配

    公开(公告)号：US07522463B2

    公开(公告)日：2009-04-21

    申请号：US11652770

    申请日：2007-01-12

    申请人： Gabriele Pelli ,  Lorenzo Bedarida ,  Massimiliano Frulio ,  Davide Manfre′

    发明人： Gabriele Pelli ,  Lorenzo Bedarida ,  Massimiliano Frulio ,  Davide Manfre′

    IPC分类号： G11C7/00

    CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C16/28 ,  G11C2207/063

    摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.

    摘要翻译： 一种用于读取存储器单元状态的读出放大器电路。 在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。 耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上 不受由第一和第二级的瞬态特性提供的电容电流分量的影响。