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    NON-VOLATILE MEMORY ARRAY ARCHITECTURE WITH JOINED WORD LINES
    3.
    发明申请
    NON-VOLATILE MEMORY ARRAY ARCHITECTURE WITH JOINED WORD LINES 有权
    具有连接字线的非易失性存储器阵列架构

    公开(公告)号：US20090109754A1

    公开(公告)日：2009-04-30

    申请号：US11928086

    申请日：2007-10-30

    申请人： Steve Schumann ,  Massimiliano Frulio ,  Simone Bartoli ,  Lorenzo Bedarida ,  Edward Shue Ching Hui

    发明人： Steve Schumann ,  Massimiliano Frulio ,  Simone Bartoli ,  Lorenzo Bedarida ,  Edward Shue Ching Hui

    IPC分类号： G11C16/04 ,  H01S4/00

    CPC分类号： G11C16/3418 ,  Y10T29/49002

    摘要： In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits. One row decoder is provided for each joined set of word lines.

    摘要翻译： 在一个实施例中，非易失性存储器阵列，其中与分离的串中的最小特征尺寸宽度F一样小的窄字线从非易失性存储器阵列向外延伸并由更宽的连接器段连接。 加入的词语提供了新的机会。 首先，可以形成为覆盖字线的金属带可以通过金属连接器部分连接到字线。 连接器部分可以用作多晶硅字线和金属带之间的接口。 相同字符串中的两个相邻字线使用这些段共享单个金属带，从而减少阵列中的段和触点的总数。 在不同的串中连接字线的多晶硅接合段的增加的宽度提供了将连接扩大超出最小特征尺寸的机会，使得可以容易地在金属带和多晶硅字线之间进行接触。 第二，连接的字线需要更少的行解码器电路。 为每个连接的字线组提供一行解码器。

    NAND-LIKE MEMORY ARRAY EMPLOYING HIGH-DENSITY NOR-LIKE MEMORY DEVICES
    4.
    发明申请
    NAND-LIKE MEMORY ARRAY EMPLOYING HIGH-DENSITY NOR-LIKE MEMORY DEVICES 审中-公开
    NAND型存储器阵列采用高密度NOR形存储器件

    公开(公告)号：US20080232169A1

    公开(公告)日：2008-09-25

    申请号：US11688740

    申请日：2007-03-20

    申请人： Massimiliano Frulio ,  Lorenzo Bedarida ,  Simone Bartoli ,  Fabio Tassan Caser

    发明人： Massimiliano Frulio ,  Lorenzo Bedarida ,  Simone Bartoli ,  Fabio Tassan Caser

    IPC分类号： G11C11/34

    CPC分类号： G11C16/08 ,  G11C5/025 ,  G11C5/063

    摘要： A flash memory integrated circuit includes a plurality of flash memory arrays. A global word line driver is associated with each array, each global word line driver coupled to a plurality of select lines. A plurality of sense amplifiers are individually coupled to a plurality of bit lines. A plurality of sub arrays in each array each include a plurality of NAND flash memory cells coupled to local word lines and local bit lines. A local word line driver is associated with each sub-array and coupled to the plurality of select lines and configured to drive ones of the local word lines in its sub array associated with selected ones of the plurality of NAND flash memory cells in its sub-array. A local bit line driver is coupled between selected ones of the local bit lines in each sub array and selected ones of the plurality of bit lines.

    摘要翻译： 闪存集成电路包括多个闪存阵列。 全局字线驱动器与每个阵列相关联，每个全局字线驱动器耦合到多个选择线。 多个读出放大器分别耦合到多个位线。 每个阵列中的多个子阵列每个包括耦合到本地字线和局部位线的多个NAND快闪存储器单元。 本地字线驱动器与每个子阵列相关联并且耦合到多个选择线，并且被配置为驱动其子阵列中的与本发明的子阵列中的多个NAND快闪存储器单元中的选定的一个相关联的本地字线中的一个， 数组。 局部位线驱动器耦合在每个子阵列中的局部位线中的选定的位线和多个位线中的选定的位线之间。

    Non-volatile memory array architecture with joined word lines
    5.
    发明授权
    Non-volatile memory array architecture with joined word lines 有权
    具有连接字线的非易失性存储器阵列架构

    公开(公告)号：US07684245B2

    公开(公告)日：2010-03-23

    申请号：US11928086

    申请日：2007-10-30

    申请人： Steve Schumann ,  Massimiliano Frulio ,  Simone Bartoli ,  Lorenzo Bedarida ,  Edward Shue-Ching Hui

    发明人： Steve Schumann ,  Massimiliano Frulio ,  Simone Bartoli ,  Lorenzo Bedarida ,  Edward Shue-Ching Hui

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C5/06

    CPC分类号： G11C16/3418 ,  Y10T29/49002

    摘要： In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits. One row decoder is provided for each joined set of word lines.

    摘要翻译： 在一个实施例中，非易失性存储器阵列，其中与分离的串中的最小特征尺寸宽度F一样小的窄字线从非易失性存储器阵列向外延伸并由更宽的连接器段连接。 加入的词语提供了新的机会。 首先，可以形成为覆盖字线的金属带可以通过金属连接器部分连接到字线。 连接器部分可以用作多晶硅字线和金属带之间的接口。 相同字符串中的两个相邻字线使用这些段共享单个金属带，从而减少阵列中的段和触点的总数。 在不同的串中连接字线的多晶硅接合段的增加的宽度提供了将连接扩大超出最小特征尺寸的机会，使得可以容易地在金属带和多晶硅字线之间进行接触。 第二，连接的字线需要更少的行解码器电路。 为每个连接的字线组提供一行解码器。

    Compensated current offset in a sensing circuit
    10.
    发明申请
    Compensated current offset in a sensing circuit 有权
    感测电路中的补偿电流偏移

    公开(公告)号：US20080170455A1

    公开(公告)日：2008-07-17

    申请号：US11652742

    申请日：2007-01-12

    申请人： Lorenzo Bedarida ,  Gabriele Pelli ,  Simone Bartoli ,  Mauro Chinosi

    发明人： Lorenzo Bedarida ,  Gabriele Pelli ,  Simone Bartoli ,  Mauro Chinosi

    IPC分类号： G11C7/08

    CPC分类号： G11C7/062 ,  G11C7/02 ,  G11C7/067 ,  G11C16/26 ,  G11C2207/063

    摘要： A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.

    摘要翻译： 具有电流偏移功能的感测电路。 在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。 感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。 感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。 根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。