公开(公告)号：US08797770B2

公开(公告)日：2014-08-05

申请号：US13312879

申请日：2011-12-06

申请人： Matteo Conta ,  Lorenzo Crespi

发明人： Matteo Conta ,  Lorenzo Crespi

IPC分类号： H02M3/18

CPC分类号： H02M3/07 ,  H02M2001/0035 ,  H02M2001/0045 ,  Y02B70/16

摘要： A capacitive voltage converter comprising a switched capacitor array having a voltage input and a voltage output. A skip gating control coupled to the switched capacitor array and configured to control a switching activity of the switched capacitor array. A resistance look-up table coupled to the switched capacitor array and configured to control a resistance value of the switched capacitor array.

摘要翻译： 一种电容式电压转换器，包括具有电压输入和电压输出的开关电容器阵列。 耦合到开关电容器阵列并被配置为控制开关电容器阵列的开关活动的跳闸选通控制。 耦合到开关电容器阵列并被配置为控制开关电容器阵列的电阻值的电阻查找表。

公开(公告)号：US20130141071A1

公开(公告)日：2013-06-06

申请号：US13312879

申请日：2011-12-06

申请人： Matteo Conta ,  Lorenzo Crespi

发明人： Matteo Conta ,  Lorenzo Crespi

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  H02M2001/0035 ,  H02M2001/0045 ,  Y02B70/16

摘要： A capacitive voltage converter comprising a switched capacitor array having a voltage input and a voltage output. A skip gating control coupled to the switched capacitor array and configured to control a switching activity of the switched capacitor array. A resistance look-up table coupled to the switched capacitor array and configured to control a resistance value of the switched capacitor array.

摘要翻译： 一种电容式电压转换器，包括具有电压输入和电压输出的开关电容器阵列。 耦合到开关电容器阵列并被配置为控制开关电容器阵列的开关活动的跳闸选通控制。 耦合到开关电容器阵列并被配置为控制开关电容器阵列的电阻值的电阻查找表。

公开(公告)号：US06265944B1

公开(公告)日：2001-07-24

申请号：US09405766

申请日：1999-09-27

申请人： Matteo Conta ,  Akbar Ali

发明人： Matteo Conta ,  Akbar Ali

IPC分类号： H03F345

CPC分类号： H03F3/45188 ,  H03F2203/45544 ,  H03F2203/45554 ,  H03F2203/45594 ,  H03F2203/45631 ,  H03F2203/45702

摘要： RF voltage amplifier circuits which have high voltage amplifier gain and input signal frequency range, and a method for boosting the voltage amplifier gain and input signal frequency range in such circuits is provided. A method includes the steps of providing a voltage amplifier having a transistor with the grounded source and the drain connected to a power supply via a resistive load, and providing an integrated inductor for biasing the transistor, having an inductor connecting an input signal terminal to the gate of the transistor and a capacitor connecting the gate and the source of the transistor. The next step includes selecting a resonant frequency of the integrated inductor at a frequency where the voltage amplifier gain is starting to roll-off, for boosting the voltage amplifier gain and the input signal frequency range. The integrated inductor preferably operates at a resonant frequency approximately matching the roll-off frequency of the voltage amplifier. In another embodiment the voltage amplifier has a common emitter (CE) gain stage, a common base (CB) cascade stage directly-coupled to the CE gain stage, and a constant current mirror source. The integrated inductor has two inductors, each connected to one input of the amplifier input signal pair and a capacitor connecting the inductors. This circuit can be adapted for fully differential operation mode or for single ended operation mode.

摘要翻译： 提供具有高电压放大器增益和输入信号频率范围的RF电压放大器电路，以及用于升高这些电路中的电压放大器增益和输入信号频率范围的方法。 一种方法包括以下步骤：提供具有晶体管的电压放大器，其中接地源极和漏极经由电阻性负载连接到电源，并且提供用于偏置晶体管的集成电感器，其具有将输入信号端子连接到 晶体管的栅极和连接晶体管的栅极和源极的电容器。 下一步包括以电压放大器增益开始滚降的频率选择集成电感器的谐振频率，以升高电压放大器增益和输入信号频率范围。 集成电感器优选以大致匹配电压放大器的滚降频率的谐振频率工作。 在另一个实施例中，电压放大器具有公共发射极（CE）增益级，直接连接到CE增益级的公共基极（CB）级联级和恒定电流镜源。 集成电感器具有两个电感器，每个电感器连接到放大器输入信号对的一个输入端和连接电感器的电容器。 该电路可适用于全差分运行模式或单端运行模式。

公开(公告)号：US07626469B2

公开(公告)日：2009-12-01

申请号：US12105042

申请日：2008-04-17

申请人： Ramesh Chokkalingam ,  Matteo Conta

发明人： Ramesh Chokkalingam ,  Matteo Conta

IPC分类号： H03B1/04 ,  H03L7/085

CPC分类号： H03L7/0895 ,  H03L7/093

摘要： An electric circuit, for use in a phase lock loop circuit, the electric circuit comprising: a first circuit element, being a phase frequency detector or a charge pump; at least one LC resonant loop, the first circuit element forming part of the loop; and means arranged to reduce ringing in said at least one LC resonant loop.

摘要翻译： 一种用于锁相环电路的电路，所述电路包括：第一电路元件，是相位频率检测器或电荷泵; 至少一个LC谐振回路，所述第一电路元件形成所述环路的一部分; 以及用于减少所述至少一个LC谐振回路中的振铃的装置。

公开(公告)号：US20080214139A1

公开(公告)日：2008-09-04

申请号：US11795745

申请日：2006-09-26

申请人： Matteo Conta ,  Valentina Della Torre ,  Francesco Svelto ,  Giuseppe Cusmai

发明人： Matteo Conta ,  Valentina Della Torre ,  Francesco Svelto ,  Giuseppe Cusmai

IPC分类号： H04B1/16 ,  H03G3/10

CPC分类号： H03F1/26 ,  H03F1/22 ,  H03F3/195 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/42 ,  H03F2200/48 ,  H03F2200/54 ,  H04B1/18 ,  H04B1/3805

摘要： A radio-frequency receiver for, e.g., receiving GPS signals in a cellular telephone has an input, a first gain stage in the form of a linear low noise amplifier with voltage-voltage feedback and a resonant load, and a second gain stage based on a common source input transconductor. Associated with the input and the first gain stage is a filter comprising a notch filter part for rejecting an interfering signal, e.g. a cell phone transmitter signal, and, connected between the parallel resonant circuit and the input, a series capacitance which, in combination with the inductor of the parallel-resonant circuit, forms a series-resonant circuit to provide a low impedance path at a wanted signal frequency.

摘要翻译： 用于例如在蜂窝电话中接收GPS信号的射频接收机具有输入，具有电压 - 电压反馈和谐振负载的线性低噪声放大器形式的第一增益级和基于 一个共同的源输入跨导体。 与输入和第一增益级相关联的是包括用于拒绝干扰信号的陷波滤波器部分的滤波器，例如， 一个手机发射机信号，并且连接在并联谐振电路和输入端之间，串联电容与并联谐振电路的电感器组合形成一个串联谐振电路，以在想要的时候提供一个低阻抗路径 信号频率。

公开(公告)号：US20080157864A1

公开(公告)日：2008-07-03

申请号：US11795746

申请日：2006-09-25

申请人： Matteo Conta ,  Andrea Baschirotto ,  Stefano D'Amico

发明人： Matteo Conta ,  Andrea Baschirotto ,  Stefano D'Amico

IPC分类号： H04B1/10

CPC分类号： H03H11/1213

摘要： The present invention addresses a need for reducing the power consumption in a baseband filter used in a front-end wireless receiver while providing the necessary linearity. In particular, relatively high linearity can be obtained with lower power consumption than has heretofore been the case. This is achieved in embodiments of the invention using an optimized single-branch fully differential structure which operates as a “composite” source-follower (when using CMOS devices) with an ideal unitary dc gain. A positive feedback internal to the source follower allows one to synthesize two complex-poles.

摘要翻译： 本发明解决了在提供必要的线性度的同时降低在前端无线接收机中使用的基带滤波器的功耗的需要。 特别地，与迄今为止相比，能够以更低的功耗获得相对高的线性度。 这在本发明的实施例中使用优化的单分支完全差分结构来实现，该单分支全差分结构作为具有理想单位直流增益的“复合”源极跟随器（当使用CMOS器件时）工作。 来源跟随器内部的正反馈允许一个合成两个复极点。

公开(公告)号：US08013684B2

公开(公告)日：2011-09-06

申请号：US12204546

申请日：2008-09-04

申请人： Matteo Conta ,  Andrea Baschirotto

发明人： Matteo Conta ,  Andrea Baschirotto

IPC分类号： H04B3/30 ,  H03H7/00

CPC分类号： H01L23/642 ,  H01L23/552 ,  H01L23/645 ,  H01L23/66 ,  H01L2223/6688 ,  H01L2924/0002 ,  H01L2924/19104 ,  H01L2924/3011 ,  H01L2924/00

摘要： In an integrated circuit having a number of circuit units on a single semiconductor chip, particularly in a system-on-chip integrated circuit including an integrated transceiver, interference between the circuit units is suppressed using on-chip resonant elements. Each resonant element has at least one on-chip capacitor and at least one on-chip conductive line constituting an inductance. The capacitance-inductance combinations are arranged to be resonant at one or more frequencies at which radio frequency energy is generated by the circuit units. The capacitive part of each series resonant combination is formed as a plurality of capacitor elements forming in an array to minimise self-inductance. Also disclosed is a filtering arrangement in which each circuit unit is individually supplied from the tap of a series resistive-capacitance combination to provide low-pass filtering. The resistance of such a combination may be configured as an FET to allow the circuit unit to be individually powered down to a low leakage state.

摘要翻译： 在具有单个半导体芯片上的多个电路单元的集成电路中，特别是在包括集成收发器的片上系统集成电路中，使用片上谐振元件来抑制电路单元之间的干扰。 每个谐振元件具有至少一个片上电容器和构成电感的至少一个片上导线。 电容 - 电感组合被布置为在电路单元产生射频能量的一个或多个频率处谐振。 每个串联谐振组合的电容部分形成为以阵列形成的多个电容器元件以最小化自感。 还公开了一种滤波装置，其中每个电路单元从串联电阻电容组合的抽头单独提供以提供低通滤波。 这种组合的电阻可以被配置为FET，以允许电路单元被单独掉电到低泄漏状态。

公开(公告)号：US06215363B1

公开(公告)日：2001-04-10

申请号：US09405752

申请日：1999-09-27

申请人： Matteo Conta ,  Akbar Ali

发明人： Matteo Conta ,  Akbar Ali

IPC分类号： H03L7089

CPC分类号： H03L7/081 ,  H03L7/0802 ,  H03L7/0895 ,  H03L7/18

摘要： In a phase lock loop, a charge pump includes a current mirror circuit. The current mirror circuit contains a bias current source and a current mirror source which mirrors the current of the bias current source. The current mirror source is turned on and off in accordance with an output signal from a phase detector to produce correction signals for a VCO. To conserve power, circuits are provided for turning the bias current source on just before it is needed by the current mirror source and for turning the bias current source off just after the current mirror source turns off.

摘要翻译： 在锁相环中，电荷泵包括电流镜电路。 电流镜电路包含偏置电流源和反映偏置电流源的电流的电流镜源。 电流镜源根据来自相位检测器的输出信号导通和截止，以产生用于VCO的校正信号。 为了节省电力，提供电路用于在电流镜源需要之前转动偏置电流源，并且在电流镜源关闭之后关闭偏置电流源。

公开(公告)号：US06208183B1

公开(公告)日：2001-03-27

申请号：US09302755

申请日：1999-04-30

申请人： Larry B. Li ,  Akbar Ali ,  Matteo Conta

发明人： Larry B. Li ,  Akbar Ali ,  Matteo Conta

IPC分类号： H03L700

CPC分类号： H03L7/081 ,  H03L7/083 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/183

摘要： A gated-delay locked loop that generates an output clock in phase with and having a frequency which is an integer multiple of the frequency of a reference clock. The gated delay-locked loop includes a voltage-controlled gated oscillator having first and second serially connected voltage-controlled delay elements that each introduce a time delay to produce a first delayed clock and the output clock. An S-R flip-flop receives the first delayed clock on its R-input and either the output clock or the reference clock on its S-input to produce a loop clock. The loop clock is provided to the first delay element. A multiplexer selects the reference clock as the S input to the flip-flop once every N cycles, and selects the output clock as the S input the remaining N−1 cycles. A phase detector, a charge pump and a loop filter compare the phase of the output clock to the phase of the reference clock and apply a voltage to the delay elements to correct any phase differences.

摘要翻译： 门控延迟锁定环，其产生与参考时钟的频率的整数倍的频率相位并且具有频率的输出时钟。 门控延迟锁定环路包括具有第一和第二串联连接的电压控制延迟元件的电压控制选通振荡器，每个引入时间延迟以产生第一延迟时钟和输出时钟。 S-R触发器在其R输入端接收第一个延迟时钟，并在其S输入端接收输出时钟或参考时钟，以产生一个回路时钟。 环路时钟被提供给第一延迟元件。 多路复用器每N个周期选择参考时钟作为触发器的S输入，并选择输出时钟作为S输入剩余的N-1个周期。 相位检测器，电荷泵和环路滤波器将输出时钟的相位与参考时钟的相位进行比较，并向延迟元件施加电压以校正任何相位差。

公开(公告)号：US6160432A

公开(公告)日：2000-12-12

申请号：US302666

申请日：1999-04-30

申请人： Woogeun Rhee ,  Matteo Conta

发明人： Woogeun Rhee ,  Matteo Conta

IPC分类号： H03L7/089 ,  H03L7/06

CPC分类号： H03L7/0896 ,  H03L7/0895

摘要： A source-switched or gate-switched charge pump having a cascoded output. A first current-mirror comprised of p-channel CMOS transistors is coupled on one side of an output node and a second current mirror comprised of n-channel CMOS transistors is coupled on the opposite side of the output node. A reference current source is coupled between the current mirrors. A p-channel CMOS cascode transistor is coupled between the first current mirror and the output node, and an n-channel CMOS cascode transistor is coupled between the second current mirror and the output node. A p-channel CMOS transistor switch is coupled to either the source or the gate of the output transistor of the first current mirror and receives a first control signal at its gate. An n-channel CMOS transistor switch is coupled to either the source or the gate of the output transistor of the second current mirror and receives a second control signal at its gate.

摘要翻译： 具有级联输出的源极开关或栅极开关电荷泵。 由p沟道CMOS晶体管构成的第一电流镜耦合在输出节点的一侧，由n沟道CMOS晶体管构成的第二电流镜耦合在输出节点的相反侧。 参考电流源耦合在电流镜之间。 p沟道CMOS共源共栅晶体管耦合在第一电流镜和输出节点之间，并且n沟道CMOS共源共栅晶体管耦合在第二电流镜和输出节点之间。 p沟道CMOS晶体管开关耦合到第一电流镜的输出晶体管的源极或栅极，并在其栅极处接收第一控制信号。 n沟道CMOS晶体管开关耦合到第二电流镜的输出晶体管的源极或栅极，并在其栅极处接收第二控制信号。