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    Modulator, phase locked loop using the same, and method applied thereto
    1.
    发明授权
    Modulator, phase locked loop using the same, and method applied thereto 有权
    调制器，使用其的锁相环，以及应用于其的方法

    公开(公告)号：US09584143B2

    公开(公告)日：2017-02-28

    申请号：US14943129

    申请日：2015-11-17

    Applicant: MEDIATEK Inc.

    Inventor： Yi-Chieh Huang ,  Ping-Ying Wang

    IPC: H04L7/033 ,  H03L7/197 ,  H03C3/00

    CPC classification number: H03L7/1976 ,  H03C3/00 ,  H03C3/0933

    Abstract: A modulator for generating a control code in response to a frequency control word is provided. The modulator includes an adder, an accumulator, a next state generation unit, and a code generation unit. The adder generates a frequency error signal by calculating a difference between the frequency control word and the control code. The accumulator generates a phase error signal by accumulating the frequency error signal. The phase error signal includes an integer part and a fractional part. The integer part of the phase error signal is a current state signal. The next state generation unit generates a next state signal according to a characteristic probability distribution determined by the fractional part of the phase error signal. The code generation unit generates the control code in response to the current state signal and the next state signal.

    Abstract translation: 提供了一种用于响应频率控制字产生控制码的调制器。 调制器包括加法器，累加器，下一个状态产生单元和代码生成单元。 加法器通过计算频率控制字和控制码之间的差异来产生频率误差信号。 累加器通过累加频率误差信号产生相位误差信号。 相位误差信号包括整数部分和小数部分。 相位误差信号的整数部分是当前状态信号。 下一个状态产生单元根据由相位误差信号的分数部分确定的特征概率分布产生下一个状态信号。 代码生成单元响应于当前状态信号和下一状态信号产生控制代码。

    Spread spectrum clock generators
    2.
    发明授权
    Spread spectrum clock generators 有权
    扩频时钟发生器

    公开(公告)号：US08531214B2

    公开(公告)日：2013-09-10

    申请号：US13744821

    申请日：2013-01-18

    Applicant: MediaTek Inc.

    Inventor： Shang-Ping Chen ,  Ping-Ying Wang

    IPC: H03D3/24

    CPC classification number: H03B19/00 ,  H03L7/081 ,  H03L7/1976

    Abstract: Spread spectrum generators and methods are disclosed. In one implementation, a spread spectrum clock generator includes a phase locked loop generating an output clock according to a first clock and a second clock; a delay line coupled between the first clock and the phase locked loop; a modulation unit providing a modulation signal to control the delay line thereby modulating phase of the first clock, such that frequency of the output clock generated by the phase locked loop varies periodically; a scaling unit scaling the modulation signal from the modulation unit according to a scaling ratio, and outputting to the delay line; and a calibration unit generating an output signal for controlling the scaling ratio.

    Abstract translation: 公开了扩频发生器和方法。 在一个实现中，扩频时钟发生器包括根据第一时钟和第二时钟产生输出时钟的锁相环; 耦合在所述第一时钟和所述锁相环之间的延迟线; 调制单元，其提供调制信号以控制延迟线，从而调制第一时钟的相位，使得由锁相环产生的输出时钟的频率周期性变化; 缩放单元，根据缩放比例从调制单元缩放调制信号，并输出到延迟线; 以及生成用于控制缩放比的输出信号的校准单元。

    MODULATOR, PHASE LOCKED LOOP USING THE SAME, AND METHOD APPLIED THERETO
    3.
    发明申请
    MODULATOR, PHASE LOCKED LOOP USING THE SAME, AND METHOD APPLIED THERETO 有权
    调制器，相位锁相环及其应用方法

    公开(公告)号：US20160211967A1

    公开(公告)日：2016-07-21

    申请号：US14943129

    申请日：2015-11-17

    Applicant: MEDIATEK Inc.

    Inventor： Yi-Chieh Huang ,  Ping-Ying Wang

    IPC: H04L7/02 ,  H03L7/093 ,  H03L7/089

    CPC classification number: H03L7/1976 ,  H03C3/00 ,  H03C3/0933

    Abstract: A modulator for generating a control code in response to a frequency control word is provided. The modulator includes an adder, an accumulator, a next state generation unit, and a code generation unit. The adder generates a frequency error signal by calculating a difference between the frequency control word and the control code. The accumulator generates a phase error signal by accumulating the frequency error signal. The phase error signal includes an integer part and a fractional part. The integer part of the phase error signal is a current state signal. The next state generation unit generates a next state signal according to a characteristic probability distribution determined by the fractional part of the phase error signal. The code generation unit generates the control code in response to the current state signal and the next state signal.

    Abstract translation: 提供了一种用于响应频率控制字产生控制码的调制器。 调制器包括加法器，累加器，下一个状态产生单元和代码生成单元。 加法器通过计算频率控制字和控制码之间的差异来产生频率误差信号。 累加器通过累加频率误差信号产生相位误差信号。 相位误差信号包括整数部分和小数部分。 相位误差信号的整数部分是当前状态信号。 下一个状态产生单元根据由相位误差信号的分数部分确定的特征概率分布产生下一个状态信号。 代码生成单元响应于当前状态信号和下一状态信号产生控制代码。

    Supply voltage drift insensitive digitally controlled oscillator and phase locked loop circuit
    4.
    发明授权
    Supply voltage drift insensitive digitally controlled oscillator and phase locked loop circuit 有权
    电源电压漂移不敏感数字控制振荡器和锁相环电路

    公开(公告)号：US09306577B2

    公开(公告)日：2016-04-05

    申请号：US13778935

    申请日：2013-02-27

    Applicant: MediaTek Inc.

    Inventor： Yi-Chieh Huang ,  Ping-Ying Wang

    IPC: H03K3/03 ,  H03L1/00 ,  H03L7/099 ,  H03L7/14

    CPC classification number: H03L1/00 ,  H03K3/0315 ,  H03L7/0995 ,  H03L7/14 ,  H03L2207/06 ,  H03L2207/08

    Abstract: A digitally controlled oscillator includes a ring oscillator and a first supplementary circuit. The ring oscillator is coupled to a supply voltage and generates a signal oscillated at an oscillating frequency. The oscillating frequency is controlled by a digital code and further varies with a supply voltage drift in a first direction. The first supplementary circuit is coupled to the ring oscillator and facilitates the oscillating frequency to vary with the supply voltage drift in a second direction reverse to the first direction.

    Abstract translation: 数字控制振荡器包括环形振荡器和第一辅助电路。 环形振荡器耦合到电源电压并产生以振荡频率振荡的信号。 振荡频率由数字代码控制，并进一步随第一方向的电源电压漂移而变化。 第一辅助电路耦合到环形振荡器，并且促使振荡频率随着与第一方向相反的第二方向上的电源电压漂移而变化。

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