公开(公告)号：US06383941B1

公开(公告)日：2002-05-07

申请号：US09611085

申请日：2000-07-06

申请人： Meihua Shen ,  Kenju Nishikido ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Meihua Shen ,  Kenju Nishikido ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L2100

CPC分类号： H01L21/31138 ,  H01L21/0276 ,  H01L21/3065

摘要： The present disclosure relates to semiconductor processing, and to the plasma etching of organic layers, and in particular antireflective coating layers. We have discovered a particular combination of gases useful in producing chemically reactive plasma species, which provides unexpected control over etched feature critical dimension, etch profile, and uniformity of etch across a substrate surface, despite a difference in the spacing of etched features over the substrate surface. The combination of gases which produces chemically reactive plasma species consists essentially of CxHyFz, a bromine-comprising compound (which is typically HBr), and O2, where x ranges from 1 to 4, y ranges from 0 to 3, and z ranges from 1 to 10. Oxygen atoms may be substituted for hydrogen atoms in the CxHyFz compound to a limited extent Essentially inert gases which do not produce chemically reactive species may be added to the combination of etchant-species producing gases. A combination of CF4/HBr/O2 has been demonstrated to work well. With this combination of plasma source gases, critical Dimension (CD) uniformity control across the surface of the substrate is generally improved by using a volumetric ratio of CxHyFz:HBr ranging from about 2:1 to about 5:1, with a range of about 3:1 to about 4:1 being preferred. An increased plasma density also helps improve CD uniformity control. The volumetric ratio of (CxHyFz+HBr):O2 should range between about 1:1 to 5:1, with a range of about 2:1 to about 3:1 being preferred.

摘要翻译： 本公开涉及半导体处理，以及有机层的等离子体蚀刻，特别是抗反射涂层。 我们已经发现了可用于生产化学反应性等离子体物质的特定气体组合，尽管蚀刻特征在衬底上的间隔有差异，但是它们对蚀刻特征临界尺寸，蚀刻轮廓以及衬底表面上的蚀刻均匀性提供了意想不到的控制 表面。 产生化学反应性等离子体物质的气体的组合基本上由CxHyFz，含溴化合物（通常为HBr）和O 2组成，其中x为1至4，y为0至3，z的范围为1 氧原子可以在有限的程度上代替CxHyFz化合物中的氢原子。基本上不产生化学反应性物质的惰性气体可以添加到产生蚀刻剂的气体组合中。 CF4 / HBr / O2的组合已被证明是有效的。 通过这种等离子体源气体的组合，通常通过使用C 2 H 4 F 5 :H 2 O的体积比约2:1至约5:1的体积比来改善基底表面上的临界尺寸（CD）均匀性控制，其范围为约 优选3:1至约4:1。 增加的等离子体密度也有助于改善CD均匀性控制。 （C x H y F z + HBr）：O 2的体积比应在约1:1至5:1之间，优选约2:1至约3:1的范围。

公开(公告)号：US06270634B1

公开(公告)日：2001-08-07

申请号：US09430798

申请日：1999-10-29

申请人： Ajay Kumar ,  Anisul Khan ,  Jeffrey D Chinn ,  Dragan Podlesnik

发明人： Ajay Kumar ,  Anisul Khan ,  Jeffrey D Chinn ,  Dragan Podlesnik

IPC分类号： C23C1434

CPC分类号： H01L21/67069 ,  H01J37/321 ,  H01J37/32935 ,  H01L21/3065

摘要： This invention is directed to a method for rapid plasma etching of materials which are difficult to etch at a high rate. The method is particularly useful in plasma etching silicon nitride layers more than five microns thick. The method includes the use of a plasma source gas that includes an etchant gas and a sputtering gas. Two separate power sources are used in the etching process and the power to each power source as well as the ratio between the flow rates of the etchant gas and sputtering gas can be advantageously adjusted to obtain etch rates of silicon nitride greater than two microns per minute. Additionally, an embodiment of the method of the invention provides a two etch step process which combines a high etch rate process with a low etch rate process to achieve high throughput while minimizing the likelihood of damage to underlying layers. The first etch step of the two-step method provides a high etch rate of about two microns per minute to remove substantially all of a layer to be etched. In the second step, a low etch rate process having an etch rate below about two microns per minute is used to remove any residual material not removed by the first etch step.

摘要翻译： 本发明涉及用于快速等离子体蚀刻难以高速蚀刻的材料的方法。 该方法在等离子体蚀刻中超过5微米厚的氮化硅层特别有用。 该方法包括使用包括蚀刻剂气体和溅射气体的等离子体源气体。 在蚀刻工艺中使用两个单独的电源，并且可以有利地调整蚀刻剂气体和溅射气体的流量之间的比例，以获得大于每分钟2微米的氮化硅的蚀刻速率 。 另外，本发明的方法的一个实施例提供了两个蚀刻步骤方法，其将高蚀刻速率工艺与低蚀刻速率工艺组合以实现高通量，同时最小化对下层的损伤的可能性。 两步法的第一蚀刻步骤提供了每分钟约2微米的高蚀刻速率，以便基本上除去所有待蚀刻的层。 在第二步骤中，使用蚀刻速率低于每分钟约2微米的低蚀刻速率工艺来去除通过第一蚀刻步骤未被去除的任何残留材料。

公开(公告)号：US06518192B2

公开(公告)日：2003-02-11

申请号：US10013115

申请日：2001-12-07

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L2100

CPC分类号： H01L21/30655 ,  B81B2203/033 ,  B81C1/00571 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/32137

摘要： A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as microelectrical mechanical system (“MEMS”) applications and mixed signal (i.e. analog and digital) integrated circuits, as well as other integrated circuits and devices. In one embodiment, a first etchant is used to etch through the layer in the fastest etching region, and then a second etchant is used to complete etching through the layer in the slowest etching region.

公开(公告)号：US06391788B1

公开(公告)日：2002-05-21

申请号：US09513552

申请日：2000-02-25

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L2100

CPC分类号： H01L21/30655 ,  B81B2203/033 ,  B81C1/00571 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/32137

摘要： A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

摘要翻译： 描述了用于蚀刻作为掩模结构的一部分的层的两种蚀刻剂蚀刻方法。 该方法例如在微电机械系统（MEMS）应用中以及集成电路和其它电子设备的制造中是有用的。 该方法可以有利地用于优化等离子体蚀刻工艺，该等离子体蚀刻工艺能够蚀刻具有89°+/- 1°侧壁的严格轮廓控制沟槽，该硅层形成为掩模结构的一部分，其中掩模结构引起蚀刻速率的变化。 本发明的两种蚀刻剂蚀刻方法蚀刻具有第一蚀刻剂蚀刻的结构中的层，直到蚀刻最快蚀刻区域中的层。 然后用第二蚀刻剂蚀刻该层，直到蚀刻具有最慢蚀刻速率的区域中的层。 还可以选择第二蚀刻剂以向结构的下层提供侧壁钝化和选择性。

公开(公告)号：US06372655B2

公开(公告)日：2002-04-16

申请号：US09836934

申请日：2001-04-17

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L2100

CPC分类号： H01L21/30655 ,  B81B2203/033 ,  B81C1/00571 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/32137

摘要： A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

公开(公告)号：US06802933B2

公开(公告)日：2004-10-12

申请号：US09740146

申请日：2000-12-18

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： C23F100

CPC分类号： H01L21/67069 ,  H01L21/3065 ,  H01L21/76232 ,  H01L27/1087 ,  Y10S156/916

摘要： This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.

摘要翻译： 本发明涉及一种用于蚀刻半导体衬底上的薄膜和清洗蚀刻室的方法。 该方法包括改进的处理顺序和清洁方法，其中通过用于从本基板去除暴露的材料层的蚀刻工艺来清洁由先前基板处理形成的残留物。 该方法通过将该步骤与在本发明的基底上进行的蚀刻步骤清洗来自先前基底的残余物来提供改进的基底产量。 申请人已经发现该方法在诸如DRAM堆叠的处理结构中特别有用，特别是在通过在先前硅衬底中蚀刻的沟槽形成残留物的情况下，并且从本衬底蚀刻的暴露层是氮化硅。

公开(公告)号：US06318384B1

公开(公告)日：2001-11-20

申请号：US09405349

申请日：1999-09-24

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L21302

CPC分类号： H01L21/67069 ,  H01L21/3065 ,  H01L21/76232 ,  H01L27/1087 ,  Y10S156/916

摘要： This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.

摘要翻译： 本发明涉及一种用于蚀刻半导体衬底上的薄膜和清洗蚀刻室的方法。 该方法包括改进的处理顺序和清洁方法，其中通过用于从本基板去除暴露的材料层的蚀刻工艺来清洁由先前基板处理形成的残留物。 该方法通过将该步骤与在本发明的基底上进行的蚀刻步骤清洗来自先前基底的残余物来提供改进的基底产量。 申请人已经发现该方法在诸如DRAM堆叠的处理结构中特别有用，特别是在通过在先前硅衬底中蚀刻的沟槽形成残留物的情况下，并且从本衬底蚀刻的暴露层是氮化硅。

公开(公告)号：US08652266B2

公开(公告)日：2014-02-18

申请号：US12212559

申请日：2008-09-17

申请人： Katrina Mikhaylichenko ,  Yizhak Sabba ,  Dragan Podlesnik

发明人： Katrina Mikhaylichenko ,  Yizhak Sabba ,  Dragan Podlesnik

IPC分类号： B08B3/00

CPC分类号： H01L21/67051 ,  H01L21/02071 ,  H01L21/6704 ,  H01L21/67075 ,  H01L21/67253 ,  H01L22/12 ,  H01L22/20

摘要： A system and method for removing polymer residue from around a metal gate structure formed on a surface of a substrate during a post-etch cleaning operation includes determining a plurality of process parameters associated with the metal gate structure and the polymer residue to be removed. A plurality of fabrication layers define the metal gate structure and the process parameters define characteristics of the fabrication layers and the polymer residue. A first cleaning chemistry and second cleaning chemistry are identified and a plurality of application parameters associated with the first and second cleaning chemistries are defined based on the process parameters. The first and second application chemistries are applied sequentially in a controlled manner using the application parameters to substantial remove the polymer residue while preserving the structural integrity of the gate structure.

摘要翻译： 在蚀刻前清洁操作期间从形成在基板的表面上的金属栅极结构周围除去聚合物残留物的系统和方法包括确定与金属栅极结构和待除去的聚合物残余物相关联的多个工艺参数。 多个制造层限定了金属栅极结构，并且工艺参数限定了制造层和聚合物残余物的特性。 识别第一清洁化学品和第二清洁化学品，并且基于过程参数来定义与第一和第二清洁化学品相关联的多个施用参数。 使用应用参数以受控的方式顺序施加第一和第二施用化学物质，以显着除去聚合物残余物，同时保持栅极结构的结构完整性。

公开(公告)号：US06380095B1

公开(公告)日：2002-04-30

申请号：US09716074

申请日：2000-11-16

申请人： Wei Liu ,  Yiqiong Wang ,  Maocheng Li ,  Anisul Khan ,  Shaoher Pan ,  Dragan Podlesnik

发明人： Wei Liu ,  Yiqiong Wang ,  Maocheng Li ,  Anisul Khan ,  Shaoher Pan ,  Dragan Podlesnik

IPC分类号： H01L21302

CPC分类号： H01L21/3065

摘要： The present invention pertains to an etch chemistry and method useful for the etching of silicon surfaces. The method is particularly useful in the deep trench etching of silicon where profile control is important. In the case of deep trench etching, at least a portion of the substrate toward the bottom of the trench is etched using a combination of reactive gases including a fluorine-containing compound which does not contain silicon (FC); a silicon-containing compound (SC) which does not contain fluorine; and oxygen (O2).

摘要翻译： 本发明涉及用于蚀刻硅表面的蚀刻化学和方法。 该方法在硅的深沟槽蚀刻中特别有用，其中轮廓控制是重要的。 在深沟槽蚀刻的情况下，使用包含不含硅（FC）的含氟化合物的反应性气体的组合来蚀刻朝向沟槽底部的至少一部分衬底; 不含氟的含硅化合物（SC）; 和氧气（O2）。

公开(公告)号：US06235643B1

公开(公告)日：2001-05-22

申请号：US09371966

申请日：1999-08-10

申请人： David Mui ,  Dragan Podlesnik ,  Wei Liu ,  Gene Lee ,  Nam-Hun Kim ,  Jeff Chinn

发明人： David Mui ,  Dragan Podlesnik ,  Wei Liu ,  Gene Lee ,  Nam-Hun Kim ,  Jeff Chinn

IPC分类号： H01L2100

CPC分类号： H01L21/76232 ,  H01L21/3065 ,  H01L21/3081

摘要： The present invention provides straight forward methods for plasma etching a trench having rounded top corners, or rounded bottom corners, or both in a silicon substrate. A first method for creating a rounded top corner on the etched silicon trench comprises etching both an overlying silicon oxide layer and an upper portion of the silicon substrate during a “break-through” step which immediately precedes the step in which the silicon trench is etched. The plasma feed gas for the break-through step comprises carbon and fluorine. In this method, the photoresist layer used to pattern the etch stack is preferably not removed prior to the break-through etching step. Subsequent to the break-through step, a trench is etched to a desired depth in the silicon substrate using a different plasma feed gas composition. A second method for creating a rounded top corner on the etched silicon trench comprises formation of a built-up extension on the sidewall of an overlying patterned silicon nitride hard mask during etch (break-through) of a silicon oxide adhesion layer which lies between the hard mask and a silicone substrate. The built-up extension upon the silicon nitride sidewall acts as a sacrificial masking material during etch of the silicon trench, delaying etching of the silicon at the outer edges of the top of the trench. This permits completion of trench etching with delayed etching of the top corner of the trench and provides a more gentle rounding (increased radius) at the top corners of the trench. During the etching of the silicon trench to its final dimensions, it is desirable to round the bottom corners of the finished silicon trench. We have discovered that a more rounded bottom trench corner is obtained using a two-step silicon etch process where the second step of the process is carried out at a higher process chamber pressure than the first step.

摘要翻译： 本发明提供了用于在硅衬底中等离子体蚀刻具有圆形顶角或圆形底角或两者的沟槽的直接方法。 用于在蚀刻的硅沟槽上形成圆角顶角的第一种方法包括：在“穿透”步骤​​期间蚀刻覆盖硅氧化物层和硅衬底的上部两者之间，其中硅裂纹之前的步骤 。 用于穿透步骤的等离子体进料气体包括碳和氟。 在该方法中，用于图案化蚀刻叠层的光致抗蚀剂层优选在穿透蚀刻步骤之前不被去除。 在突破步骤之后，使用不同的等离子体进料气体组合物将沟槽蚀刻到硅衬底中的所需深度。 用于在蚀刻的硅沟槽上产生圆角顶角的第二种方法包括在位于第二层之间的氧化硅粘合层的蚀刻（穿透）期间在覆盖的图案化氮化硅硬掩模的侧壁上形成积层延伸。 硬面罩和硅胶基材。 在硅氮化物侧壁上的累积延伸在硅沟槽的蚀刻期间用作牺牲掩模材料，延迟在沟槽顶部的外边缘处的硅的蚀刻。 这允许通过延迟蚀刻沟槽的顶角完成沟槽蚀刻，并且在沟槽的顶角提供更温和的圆化（增加的半径）。 在将硅沟槽蚀刻到其最终尺寸期间，期望圆形完成的硅沟槽的底角。 我们已经发现，使用两步硅蚀刻工艺获得更圆的底部沟槽角，其中该工艺的第二步骤在比第一步高的处理室压力下进行。