公开(公告)号：US20170230006A1

公开(公告)日：2017-08-10

申请号：US15019409

申请日：2016-02-09

申请人： MediaTek Inc.

发明人： Hsing-ting Yu ,  Fei Song ,  I-Chang Wu ,  YuenHui Chee ,  Chiyuan Lu ,  Keng Leong Fong ,  Osama K.A. Shana'a

IPC分类号： H03F1/02 ,  H03F3/21 ,  H03F3/193

CPC分类号： H03F1/0222 ,  H03F1/0261 ,  H03F1/0266 ,  H03F1/0277 ,  H03F1/0288 ,  H03F1/48 ,  H03F3/193 ,  H03F3/211 ,  H03F3/245 ,  H03F3/45 ,  H03F3/45071 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/72 ,  H03F2200/18 ,  H03F2200/36 ,  H03F2200/435 ,  H03F2200/451 ,  H03F2200/453 ,  H03F2200/465 ,  H03F2200/555 ,  H03F2203/21106 ,  H03F2203/45311 ,  H03F2203/45352 ,  H03F2203/45368 ,  H03F2203/45544 ,  H03F2203/45674 ,  H03F2203/7206

摘要： Methods and apparatus for providing adaptive biasing to power amplifiers. Adaptive bias circuits are configured to provide sharp turn on and/or current clamping to improve the efficiency of a power amplifier over a wide input signal bandwidth. Sharp turn on may be achieved using a subtraction technique to subtract outputs from multiple detectors. Clamping may be achieved using MOSFET device characteristics to pull the device from the triode region into the saturation, subtraction techniques to subtract the outputs from multiple detectors, and/or by using circuit devices, such as diodes.

公开(公告)号：US20090002065A1

公开(公告)日：2009-01-01

申请号：US11823079

申请日：2007-06-26

申请人： Ahmad Mirzaei ,  Hooman Darabi

发明人： Ahmad Mirzaei ,  Hooman Darabi

IPC分类号： H04B1/10

CPC分类号： H03F3/45183 ,  H03F3/19 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2203/45368 ,  H03F2203/45704

摘要： According to one exemplary embodiment, a buffer circuit for reducing differential-mode phase noise and quadrature phase error comprises first and second switching branches driven by an in-phase (I) signal, third and fourth switching branches driven by a quadrature-phase (Q) signal, the first and second switching branches and third and fourth switching branches being coupled to a common bias current source to reduce the differential-mode phase noise and quadrature phase error at an output of the buffer circuit. In one embodiment, the switching branches may be loaded by first, second, third, and fourth resonators formed, for example, by L-C circuits tuned to a local oscillator frequency. In one embodiment, the buffer circuit may comprise switching branches formed by FETs, and be used in conjunction with a local oscillator and mixer circuits to down-convert a radio frequency (RF) signal, in a receiving system, for example.

摘要翻译： 根据一个示例性实施例，用于减小差模相位噪声和正交相位误差的缓冲电路包括由同相（I）信号驱动的第一和第二开关分支，由正交相（Q）驱动的第三和第四开关分支 ）信号，第一和第二开关分支以及第三和第四开关分支耦合到公共偏置电流源，以减小缓冲电路的输出处的差模相位噪声和正交相位误差。 在一个实施例中，开关分支可以由例如由调谐到本地振荡器频率的L-C电路形成的第一，第二，第三和第四谐振器来加载。 在一个实施例中，缓冲电路可以包括由FET形成的开关支路，并且例如在接收系统中与本地振荡器和混频器电路结合使用以降低转换射频（RF）信号。

公开(公告)号：US07274253B2

公开(公告)日：2007-09-25

申请号：US11090067

申请日：2005-03-28

申请人： Meng-An Pan

发明人： Meng-An Pan

IPC分类号： H03F1/14

CPC分类号： H03F3/1935 ,  H03F3/45381 ,  H03F2203/45361 ,  H03F2203/45368 ,  H03F2203/45638 ,  H03G1/0088 ,  H03G3/3042

摘要： A transmitter includes a first variable gain amplifier (VGA) and a second VGA coupled to an output of the first VGA. The first and second VGAs each comprise a plurality of parallel gain stages. Gains of the first and second VGAs are equal to the sum of the gains of the activated parallel amplifiers within each corresponding plurality of parallel amplifiers. Each parallel amplifier comprises a parallel differential amplifier controlled by a pair of switches to activate and deactivate the parallel differential amplifier. The gains of the first and second VGAs are increased by activating additional parallel amplifiers. The gains of the first and second VGAs are decreased by deactivating additional parallel amplifiers. The variable gains of the first and second VGAs provide an extended gain control with improved local oscillator (LO) leakage interference rejection.

摘要翻译： 发射机包括耦合到第一VGA的输出的第一可变增益放大器（VGA）和第二VGA。 第一和第二VGA分别包括多个并联增益级。 第一和第二VGA的增益等于每个对应的多个并行放大器内激活的并联放大器的增益之和。 每个并联放大器包括由一对开关控制的并联差分放大器，以激活和去激活并行差分放大器。 通过激活附加的并行放大器来增加第一和第二VGA的增益。 第一和第二VGA的增益通过去激活附加并行放大器而减小。 第一和第二VGA的可变增益提供了具有改进的本地振荡器（LO）泄漏干扰抑制的扩展增益控制。

公开(公告)号：US20060214728A1

公开(公告)日：2006-09-28

申请号：US11090067

申请日：2005-03-28

申请人： Meng-An Pan

发明人： Meng-An Pan

IPC分类号： H03F1/14

CPC分类号： H03F3/1935 ,  H03F3/45381 ,  H03F2203/45361 ,  H03F2203/45368 ,  H03F2203/45638 ,  H03G1/0088 ,  H03G3/3042

摘要： A transmitter includes a first variable gain amplifier (VGA) and a second VGA coupled to an output of the first VGA. The first and second VGAs each comprise a plurality of parallel gain stages. Gains of the first and second VGAs are equal to the sum of the gains of the activated parallel amplifiers within each corresponding plurality of parallel amplifiers. Each parallel amplifier comprises a parallel differential amplifier controlled by a pair of switches to activate and deactivate the parallel differential amplifier. The gains of the first and second VGAs are increased by activating additional parallel amplifiers. The gains of the first and second VGAs are decreased by deactivating additional parallel amplifiers. The variable gains of the first and second VGAs provide an extended gain control with improved local oscillator (LO) leakage interference rejection.

公开(公告)号：US09941852B1

公开(公告)日：2018-04-10

申请号：US15278934

申请日：2016-09-28

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Firas N. Abughazaleh

IPC分类号： H03F3/45 ,  H03G1/00

CPC分类号： H03G1/0088 ,  H03F3/45183 ,  H03F3/45192 ,  H03F3/45766 ,  H03F3/45775 ,  H03F2203/45044 ,  H03F2203/45074 ,  H03F2203/45288 ,  H03F2203/45354 ,  H03F2203/45368 ,  H03F2203/45396 ,  H03G1/0029

摘要： A semiconductor device includes an operational transconductance amplifier (OTA) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the OTA. Measurement circuitry is coupled to measure offset in the OTA. Control logic is configured to operate the first and second sets of switches to couple input transistors of a first group of the configuration units to the first transistor of the matched pair of transistors, and to couple input transistors of a remaining group of the configuration units to the second transistor of the matched pair of transistors. Settings of the first and second sets of switches are selected to minimize the offset.

公开(公告)号：US20180052205A1

公开(公告)日：2018-02-22

申请号：US15678658

申请日：2017-08-16

申请人： ATOMERA INCORPORATED

发明人： Richard Stephen ROY

IPC分类号： G01R31/319 ,  H01L27/108 ,  H01L21/66 ,  H01L29/10 ,  H01L29/15 ,  H01L29/16 ,  G11C11/4078 ,  G01R31/26 ,  G01R31/3193

CPC分类号： G01R31/2831 ,  G01R31/2644 ,  G01R31/2648 ,  G01R31/275 ,  G01R31/2894 ,  G01R31/31924 ,  G01R31/31932 ,  G11C11/4078 ,  G11C11/4087 ,  G11C29/50004 ,  H01L21/823412 ,  H01L22/34 ,  H01L27/092 ,  H01L27/10897 ,  H01L29/105 ,  H01L29/152 ,  H01L29/16 ,  H01L29/7843 ,  H01L29/7849 ,  H03F3/45183 ,  H03F2200/453 ,  H03F2203/45361 ,  H03F2203/45368

摘要： A method for making a semiconductor device may include forming active circuitry on a substrate including differential transistor pairs, and forming threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors each includes spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Moreover, each of the channel regions may include a superlattice.

公开(公告)号：US07688143B2

公开(公告)日：2010-03-30

申请号：US12081092

申请日：2008-04-10

申请人： Katsuji Kimura

发明人： Katsuji Kimura

IPC分类号： H03F3/45

CPC分类号： H03G7/06 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2203/45008 ,  H03F2203/45134 ,  H03F2203/45368 ,  H03F2203/45646 ,  H03G1/0029 ,  H03G7/00

摘要： Disclosed is a variable gain circuit including a gain change region in which the gain is changed substantially exponentially as a function of a control voltage. The gain is changed in the gain change region substantially exponentially based on a function {(1+x)2+K}/{1−x}2+K}, where x is a control voltage and K is a parameter of K≦1. The parameter K of the function is about equal to 0.21. The denominator and the numerator of the function are proportionate to driving currents of OTAs (operational transconductance amplifiers). Or, the denominator and the numerator of the above function are constituted by output currents of a MOS differential pair and a quadritail cell that includes four transistors driven by a common tail current. Outputs of two of the transistors, receiving a differential input voltage, are connected in common and outputs of the other two of the transistors, receiving the common mode voltage of the differential input voltage, are connected in common.

摘要翻译： 公开了一种可变增益电路，其包括增益变化区域，其中增益作为控制电压的函数以指数方式改变。 基于函数{（1 + x）2 + K} / {1-x} 2 + K}，增益变化区域大致呈指数变化，其中x为控制电压，K为K＆nlE的参数; 1。 函数的参数K大约等于0.21。 功能的分母和分子与OTAs（运算跨导放大器）的驱动电流成正比。 或者，上述功能的分母和分子由MOS差分对和包括由共同尾电流驱动的四个晶体管的四边形单元的输出电流构成。 接收差分输入电压的两个晶体管的输出连接在一起，另外两个晶体管的输出端接收差分输入电压的共模电压，共同连接。

公开(公告)号：US20080007339A1

公开(公告)日：2008-01-10

申请号：US11902020

申请日：2007-09-18

申请人： Meng-An Pan

发明人： Meng-An Pan

IPC分类号： H03F3/45

CPC分类号： H03F3/1935 ,  H03F3/45381 ,  H03F2203/45361 ,  H03F2203/45368 ,  H03F2203/45638 ,  H03G1/0088 ,  H03G3/3042

摘要： A transmitter includes a first variable gain amplifier (VGA) and a second VGA coupled to an output of the first VGA. The first and second VGAs each comprise a plurality of parallel gain stages. Gains of the first and second VGAs are equal to the sum of the gains of the activated parallel amplifiers within each corresponding plurality of parallel amplifiers. Each parallel amplifier comprises a parallel differential amplifier controlled by a pair of switches to activate and deactivate the parallel differential amplifier. The gains of the first and second VGAs are increased by activating additional parallel amplifiers. The gains of the first and second VGAs are decreased by deactivating additional parallel amplifiers. The variable gains of the first and second VGAs provide an extended gain control with improved local oscillator (LO) leakage interference rejection.

摘要翻译： 发射机包括耦合到第一VGA的输出的第一可变增益放大器（VGA）和第二VGA。 第一和第二VGA分别包括多个并联增益级。 第一和第二VGA的增益等于每个对应的多个并行放大器内激活的并联放大器的增益之和。 每个并联放大器包括由一对开关控制的并联差分放大器，以激活和去激活并行差分放大器。 通过激活附加的并行放大器来增加第一和第二VGA的增益。 第一和第二VGA的增益通过去激活附加并行放大器而减小。 第一和第二VGA的可变增益提供了具有改进的本地振荡器（LO）泄漏干扰抑制的扩展增益控制。

公开(公告)号：US20060279338A1

公开(公告)日：2006-12-14

申请号：US11150448

申请日：2005-06-10

申请人： Matthew Rowley

发明人： Matthew Rowley

IPC分类号： H03B21/00

CPC分类号： H03F3/45183 ,  H03F2203/45368 ,  H03F2203/45644 ,  H03F2203/45674

摘要： The fully differential large swing variable gain amplifier circuit includes: a first 5-transistor transconductor having a common mode node; and a second 5-transistor transconductor having a common mode node coupled to the common mode node of the first 5-transistor transconductor, wherein the second 5-transistor transconductor operates 180 degrees out of phase with the first 5-transistor transconductor.

摘要翻译： 全差分大摆动可变增益放大器电路包括：具有共模节点的第一5晶体管跨导体; 以及具有耦合到所述第一5晶体管跨导体的共模节点的共模节点的第二5晶体管跨导体，其中所述第二5晶体管跨导体与所述第一5晶体管跨导体相差180度异相。

公开(公告)号：US07119617B2

公开(公告)日：2006-10-10

申请号：US10913538

申请日：2004-08-09

申请人： Hiroyuki Rokugawa ,  Takuji Yamamoto

发明人： Hiroyuki Rokugawa ,  Takuji Yamamoto

IPC分类号： H03F3/45 ,  H03F3/04

CPC分类号： H03F3/45188 ,  H03F2203/45352 ,  H03F2203/45368 ,  H03F2203/45462 ,  H03F2203/45554

摘要： A differential amplifier suitably adapted to an ultra-high-speed signal transmitting apparatus. The differential amplifier includes a first inductor located between a differential transistor and a gate grounded transistor, an optional second inductor located between a load resistor and a power supply, and an optional third inductor located between a source follower transistor and an output terminal.

摘要翻译： 适合于超高速信号发送装置的差分放大器。 差分放大器包括位于差分晶体管和栅极接地晶体管之间的第一电感器，位于负载电阻器和电源之间的可选的第二电感器，以及位于源极跟随器晶体管和输出端子之间的可选的第三电感器。