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    Method for forming a via in a substrate and substrate with a via
    1.
    发明授权
    Method for forming a via in a substrate and substrate with a via 有权
    在具有通孔的基板和基板中形成通孔的方法

    公开(公告)号：US08471156B2

    公开(公告)日：2013-06-25

    申请号：US12583949

    申请日：2009-08-28

    Applicant: Meng-Jen Wang ,  Kuo-Pin Yang

    Inventor： Meng-Jen Wang ,  Kuo-Pin Yang

    IPC: H05K1/11

    CPC classification number: H05K3/445 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H05K3/061 ,  H05K2203/0323 ,  H05K2203/1476 ,  H01L2924/00

    Abstract: The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method includes the following steps: (a) providing a substrate; (b) forming a groove on a first surface of the substrate; (c) forming a conductive metal on the groove so as to form a central groove; (d) forming an annular groove that surrounds the conductive metal; (e) forming an insulating material in the central groove and the annular; groove; and (f) removing part of the substrate to expose the conductive metal and the insulating material.

    Abstract translation: 本发明涉及一种用于在基板和具有通孔的基板上形成通孔的方法。 该方法包括以下步骤：（a）提供衬底; （b）在所述基板的第一表面上形成凹槽; （c）在槽上形成导电金属以形成中心槽; （d）形成围绕所述导电金属的环形槽; （e）在中央槽和环形中形成绝缘材料; 槽; 和（f）去除衬底的一部分以暴露导电金属和绝缘材料。

    Method for forming a via in a substrate and substrate with a via
    3.
    发明申请
    Method for forming a via in a substrate and substrate with a via 有权
    在具有通孔的基板和基板中形成通孔的方法

    公开(公告)号：US20110048788A1

    公开(公告)日：2011-03-03

    申请号：US12583949

    申请日：2009-08-28

    Applicant: Meng-Jen Wang ,  Kuo-Pin Yang

    Inventor： Meng-Jen Wang ,  Kuo-Pin Yang

    IPC: H05K1/11 ,  H01B13/00

    CPC classification number: H05K3/445 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H05K3/061 ,  H05K2203/0323 ,  H05K2203/1476 ,  H01L2924/00

    Abstract: The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method includes the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove that has a side wall and a bottom wall on the first surface of the substrate; (c) forming a conductive metal on the side wall and the bottom wall of the groove so as to form a central groove; (d) forming an annular groove that surrounds the conductive metal on the first surface of the substrate; (e) forming an insulating material in the central groove and the annular groove; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material.

    Abstract translation: 本发明涉及一种用于在基板和具有通孔的基板上形成通孔的方法。 该方法包括以下步骤：（a）提供具有第一表面和第二表面的基底; （b）在所述基板的第一表面上形成具有侧壁和底壁的凹槽; （c）在槽的侧壁和底壁上形成导电金属，以形成中心槽; （d）形成围绕所述基板的第一表面上的所述导电金属的环形槽; （e）在所述中央槽和所述环形槽中形成绝缘材料; 和（f）去除衬底的第二表面的一部分以暴露导电金属和绝缘材料。

    CARRIER BONDING AND DETACHING PROCESSES FOR A SEMICONDUCTOR WAFER
    7.
    发明申请
    CARRIER BONDING AND DETACHING PROCESSES FOR A SEMICONDUCTOR WAFER 有权
    用于半导体波形的载体接合和分离工艺

    公开(公告)号：US20120052654A1

    公开(公告)日：2012-03-01

    申请号：US13216063

    申请日：2011-08-23

    Applicant: Kuo-Pin Yang ,  Wei-Min Hsiao ,  Cheng-Hui Hung

    Inventor： Kuo-Pin Yang ,  Wei-Min Hsiao ,  Cheng-Hui Hung

    IPC: H01L21/302 ,  B32B37/02 ,  H01L21/677 ,  B32B37/12

    CPC classification number: H01L21/6835 ,  H01L21/486 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10T156/10

    Abstract: The present invention provides a temporary carrier bonding and detaching process. A first surface of a semiconductor wafer is mounted on a first carrier by a first adhesive layer, and a first isolation coating disposed between the first adhesive layer and the first carrier. Then, a second carrier is mounted on the second surface of the semiconductor wafer. The first carrier is detached. Then, the first surface of the semiconductor wafer is mounted on a film frame. The second carrier is detached. The method of the present invention utilizes the second carrier to support and protect the semiconductor wafer, after which the first carrier is detached. Therefore, the semiconductor wafer will not be damaged or broken, thereby improving the yield rate of the semiconductor process. Furthermore, the simplicity of the detaching method for the first carrier allows for improvement in efficiency of the semiconductor process.

    Abstract translation: 本发明提供了临时的载体接合和分离工艺。 半导体晶片的第一表面通过第一粘合剂层安装在第一载体上，第一隔离涂层设置在第一粘合层和第一载体之间。 然后，第二载体安装在半导体晶片的第二表面上。 第一个承运人分离。 然后，将半导体晶片的第一表面安装在胶片框架上。 第二个承运人分离。 本发明的方法利用第二载体来支撑和保护半导体晶片，然后分离第一载体。 因此，半导体晶片不会被损坏或破损，从而提高半导体工艺的成品率。 此外，第一载体的分离方法的简单性允许提高半导体工艺的效率。

    Method for encapsulating sensor chips
    8.
    发明授权
    Method for encapsulating sensor chips 有权
    封装传感器芯片的方法

    公开(公告)号：US07563652B2

    公开(公告)日：2009-07-21

    申请号：US11617195

    申请日：2006-12-28

    Applicant: Kuo-Pin Yang ,  Wei-Min Hsiao

    Inventor： Kuo-Pin Yang ,  Wei-Min Hsiao

    IPC: H01L21/44 ,  H01L21/48

    CPC classification number: H01L21/568 ,  H01L24/97 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2224/82

    Abstract: A method for encapsulating sensor chips is disclosed. A protective layer is formed on an active surface of a sensor chip, and at least covers a sensor region in the active surface. The active surface of the sensor chip faces to a temporary carrier, so that the protective layer is attached to the temporary carrier. An encapsulant is formed on the temporary carrier to cover a back surface and side surfaces of the sensor chip. A plurality of electrically connecting components are formed in the encapsulant to electrically connect a plurality of bonding pads of the sensor chip, and then the protective layer is removed to expose the sensor region. The coverage of the protective layer is used to avoid pollution on the sensor region during encapsulating, thereby, especially in a wafer level packaging, making the package profile neat, tidy and smaller in size, and promoting production efficiency.

    Abstract translation: 公开了一种封装传感器芯片的方法。 在传感器芯片的有效表面上形成保护层，并且至少覆盖有源表面中的传感器区域。 传感器芯片的有源表面面向临时载体，使得保护层附着到临时载体上。 密封剂形成在临时载体上以覆盖传感器芯片的背面和侧表面。 在密封剂中形成多个电连接部件以电连接传感器芯片的多个接合焊盘，然后去除保护层以暴露传感器区域。 保护层的覆盖范围用于在封装期间避免对传感器区域的污染，特别是在晶片级封装中，使封装外形整齐，整齐，尺寸更小，并提高生产效率。

    Wafer level package for image sensor components and fabricating method thereof
    9.
    发明申请
    Wafer level package for image sensor components and fabricating method thereof 审中-公开
    图像传感器部件的晶片级封装及其制造方法

    公开(公告)号：US20070187711A1

    公开(公告)日：2007-08-16

    申请号：US11647408

    申请日：2006-12-29

    Applicant: Wei-Min Hsiao ,  Kuo-Pin Yang

    Inventor： Wei-Min Hsiao ,  Kuo-Pin Yang

    IPC: H01L33/00

    CPC classification number: H01L27/14618 ,  H01L27/14683 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A wafer level package for image sensor components includes an image sensor chip and several metal pillars. Several vias formed in the image sensor chip are aligned with several bonding pads. The metal pillars are formed in the vias. First ends of the metal pillars are bonded to the bonding pads. Second ends of the metal pillars protrude from a back surface of the image sensor chip. The length of the metal pillars is greater than the thickness of the image sensor chip. The image sensor chip is mounted to a printed circuit board through the metal pillars formed in the vias instead of wire bonding or redistribution line (RDL) process. There is no need to dispensing underfil between the image sensor chip and the printed circuit board to protect the metal pillars.

    Abstract translation: 用于图像传感器部件的晶片级封装包括图像传感器芯片和几个金属支柱。 在图像传感器芯片中形成的多个通孔与多个焊盘对准。 金属柱形成在通孔中。 金属柱的第一端结合到接合焊盘。 金属柱的第二端从图像传感器芯片的后表面突出。 金属柱的长度大于图像传感器芯片的厚度。 图像传感器芯片通过形成在通孔中的金属柱而不是引线键合或再分配线（RDL）工艺安装到印刷电路板。 不需要在图像传感器芯片和印刷电路板之间分配底片，以保护金属支柱。

    Method of fabricating wafer level package
    10.
    发明申请
    Method of fabricating wafer level package 有权
    制造晶圆级封装的方法

    公开(公告)号：US20060252230A1

    公开(公告)日：2006-11-09

    申请号：US11416078

    申请日：2006-05-03

    Applicant: Kuo-Pin Yang

    Inventor： Kuo-Pin Yang

    IPC: H01L21/30 ,  H01L21/46

    CPC classification number: H01L23/3114 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of fabricating wafer level package is provided. First, a wafer having a front and a rear surfaces is provided. Several fosses are then formed on the front surface of the wafer. Next, an insulative layer is formed on a surface of each fosse; a conductive layer is then formed on part of the. front surface of the wafer and the insulative layer of each fosse. A solder layer is formed on the conductive layer above each fosse. Afterward, a first substrate is attached to the front surface. Several holes are formed on the rear surface, and the holes baring the solder layer are positioned corresponding to the fosses. Then, a second substrate is attached to the rear surface of the wafer. The second substrate has several conductive pillars correspondingly inserted into the holes for connecting the solder layers. Next, the conductive structures are formed on the second substrate.

    Abstract translation: 提供了制造晶片级封装的方法。 首先，提供具有前表面和后表面的晶片。 然后在晶片的前表面上形成几个藓类。 接下来，在每个顶部的表面上形成绝缘层; 然后在其一部分上形成导电层。 晶片的前表面和每个晶片的绝缘层。 在每个顶部上的导电层上形成焊料层。 之后，将第一基板安装到前表面。 在后表面上形成几个孔，并且对应于釉料定位焊接焊料层的孔。 然后，将第二基板安装在晶片的后表面。 第二基板具有相应地插入到用于连接焊料层的孔中的几个导电柱。 接下来，在第二基板上形成导电结构。

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