公开(公告)号：US20110048788A1

公开(公告)日：2011-03-03

申请号：US12583949

申请日：2009-08-28

Applicant: Meng-Jen Wang ,  Kuo-Pin Yang

Inventor： Meng-Jen Wang ,  Kuo-Pin Yang

IPC: H05K1/11 ,  H01B13/00

CPC classification number: H05K3/445 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H05K3/061 ,  H05K2203/0323 ,  H05K2203/1476 ,  H01L2924/00

Abstract: The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method includes the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove that has a side wall and a bottom wall on the first surface of the substrate; (c) forming a conductive metal on the side wall and the bottom wall of the groove so as to form a central groove; (d) forming an annular groove that surrounds the conductive metal on the first surface of the substrate; (e) forming an insulating material in the central groove and the annular groove; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material.

Abstract translation: 本发明涉及一种用于在基板和具有通孔的基板上形成通孔的方法。 该方法包括以下步骤：（a）提供具有第一表面和第二表面的基底; （b）在所述基板的第一表面上形成具有侧壁和底壁的凹槽; （c）在槽的侧壁和底壁上形成导电金属，以形成中心槽; （d）形成围绕所述基板的第一表面上的所述导电金属的环形槽; （e）在所述中央槽和所述环形槽中形成绝缘材料; 和（f）去除衬底的第二表面的一部分以暴露导电金属和绝缘材料。

公开(公告)号：US20070252261A1

公开(公告)日：2007-11-01

申请号：US11612457

申请日：2006-12-18

Applicant: Meng-Jen Wang ,  Kuo-Pin Yang ,  Sheng-Yang Peng ,  Wei-Min Hsiao

Inventor： Meng-Jen Wang ,  Kuo-Pin Yang ,  Sheng-Yang Peng ,  Wei-Min Hsiao

IPC: H01L23/02

CPC classification number: H01L23/04 ,  B81B7/0077 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16151 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to a semiconductor device package, comprising a carrier, a first semiconductor device, a second semiconductor device, a plurality of conductive elements, a pre-mold and a lid. The first semiconductor device is electrically connected to the carrier. The second semiconductor device is disposed above the first semiconductor device. The conductive elements are used for electrically connecting the second semiconductor device and the carrier. The pre-mold and the carrier form an accommodating space for accommodating the first semiconductor device, the second semiconductor device and the conductive elements. The lid is adhered to the pre-mold for covering the opening of the pre-mold. As a result, the pre-mold is formed by molding, the manufacture process of the present invention is simpler than that of the conventional semiconductor device package.

Abstract translation: 本发明涉及一种半导体器件封装，包括载体，第一半导体器件，第二半导体器件，多个导电元件，预模具和盖子。 第一半导体器件电连接到载体。 第二半导体器件设置在第一半导体器件的上方。 导电元件用于电连接第二半导体器件和载体。 预模具和载体形成用于容纳第一半导体器件，第二半导体器件和导电元件的容纳空间。 盖子粘附到预模具以覆盖预模具的开口。 结果，通过模制形成预模具，本发明的制造工艺比传统的半导体器件封装简单。

公开(公告)号：US08471156B2

公开(公告)日：2013-06-25

申请号：US12583949

申请日：2009-08-28

Applicant: Meng-Jen Wang ,  Kuo-Pin Yang

Inventor： Meng-Jen Wang ,  Kuo-Pin Yang

IPC: H05K1/11

CPC classification number: H05K3/445 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H05K3/061 ,  H05K2203/0323 ,  H05K2203/1476 ,  H01L2924/00

Abstract: The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method includes the following steps: (a) providing a substrate; (b) forming a groove on a first surface of the substrate; (c) forming a conductive metal on the groove so as to form a central groove; (d) forming an annular groove that surrounds the conductive metal; (e) forming an insulating material in the central groove and the annular; groove; and (f) removing part of the substrate to expose the conductive metal and the insulating material.

Abstract translation: 本发明涉及一种用于在基板和具有通孔的基板上形成通孔的方法。 该方法包括以下步骤：（a）提供衬底; （b）在所述基板的第一表面上形成凹槽; （c）在槽上形成导电金属以形成中心槽; （d）形成围绕所述导电金属的环形槽; （e）在中央槽和环形中形成绝缘材料; 槽; 和（f）去除衬底的一部分以暴露导电金属和绝缘材料。

公开(公告)号：US20080087987A1

公开(公告)日：2008-04-17

申请号：US11772243

申请日：2007-07-02

Applicant: Meng-Jen Wang ,  Kuo-Pin Yang ,  Wei-Min Hsiao ,  Sheng-Yang Peng

Inventor： Meng-Jen Wang ,  Kuo-Pin Yang ,  Wei-Min Hsiao ,  Sheng-Yang Peng

IPC: H01L23/552

CPC classification number: H01L23/552 ,  B81B7/0064 ,  B81B2201/0257 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49107 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00014

Abstract: A semiconductor packaging structure having electromagnetic shielding function is disclosed, in which the packaging structure includes a carrier and a semiconductor substrate disposed thereon. The semiconductor substrate has a patterned passivation layer and a patterned metal layer disposed thereon, in which the patterned metal layer is electrically connected to at least a grounding pad of the carrier via a wire, whereby possessing the semiconductor packaging structure to have electromagnetic shielding function. A method for manufacturing a semiconductor packaging structure having electromagnetic shielding function is also disclosed in the present invention.

Abstract translation: 公开了一种具有电磁屏蔽功能的半导体封装结构，其中封装结构包括载体和设置在其上的半导体衬底。 半导体衬底具有图案化的钝化层和设置在其上的图案化金属层，其中图案化的金属层经由导线电连接到载体的至少接地焊盘，由此具有半导体封装结构以具有电磁屏蔽功能。 本发明还公开了一种具有电磁屏蔽功能的半导体封装结构的制造方法。

公开(公告)号：US07573124B2

公开(公告)日：2009-08-11

申请号：US11772243

申请日：2007-07-02

Applicant: Meng-Jen Wang ,  Kuo-Pin Yang ,  Wei-Min Hsiao ,  Sheng-Yang Peng

Inventor： Meng-Jen Wang ,  Kuo-Pin Yang ,  Wei-Min Hsiao ,  Sheng-Yang Peng

IPC: H01L23/552

CPC classification number: H01L23/552 ,  B81B7/0064 ,  B81B2201/0257 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49107 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00014

Abstract: A semiconductor packaging structure having electromagnetic shielding function is disclosed, in which the packaging structure includes a carrier and a semiconductor substrate disposed thereon. The semiconductor substrate has a patterned passivation layer and a patterned metal layer disposed thereon, in which the patterned metal layer is electrically connected to at least a grounding pad of the carrier via a wire, whereby possessing the semiconductor packaging structure to have electromagnetic shielding function. A method for manufacturing a semiconductor packaging structure having electromagnetic shielding function is also disclosed in the present invention.

Abstract translation: 公开了一种具有电磁屏蔽功能的半导体封装结构，其中封装结构包括载体和设置在其上的半导体衬底。 半导体衬底具有图案化的钝化层和设置在其上的图案化金属层，其中图案化的金属层经由导线电连接到载体的至少接地焊盘，由此具有半导体封装结构以具有电磁屏蔽功能。 本发明还公开了一种具有电磁屏蔽功能的半导体封装结构的制造方法。

公开(公告)号：US08524602B2

公开(公告)日：2013-09-03

申请号：US12876721

申请日：2010-09-07

Applicant: Meng-Jen Wang

Inventor： Meng-Jen Wang

IPC: H01L21/44

CPC classification number: H01L21/76898

Abstract: The present invention relates to a method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even.

Abstract translation: 本发明涉及一种在衬底中形成通孔的方法，包括以下步骤：（a）提供具有第一表面和第二表面的衬底; （b）在基板上形成凹槽; （c）用导电金属填充凹槽; （d）去除围绕所述导电金属的所述衬底的一部分，其中所述导电金属被保持以在所述导电金属和所述衬底之间形成容纳空间; （e）在容纳空间中形成绝缘材料; 和（f）去除衬底的第二表面的一部分以暴露导电金属和绝缘材料。 以这种方式，可以在容纳空间中形成更厚的绝缘材料，并且容纳空间中的绝缘材料的厚度是均匀的。

公开(公告)号：US08486829B2

公开(公告)日：2013-07-16

申请号：US13720559

申请日：2012-12-19

Applicant: Chi-Tsung Chiu ,  Ying-Te Ou ,  Meng-Jen Wang

Inventor： Chi-Tsung Chiu ,  Ying-Te Ou ,  Meng-Jen Wang

IPC: H01L21/44

CPC classification number: H01L21/486 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The present invention relates to a semiconductor element having a conductive via and a method for making the same and a package having a semiconductor element with a conductive via. The semiconductor element includes a silicon chip and at least one conductive via. The silicon chip includes a silicon substrate and an active circuit layer. The active circuit layer is disposed on a second surface of the silicon substrate, and has at least one metal layer. The conductive via penetrates the silicon substrate, and includes a conductive metal, The conductive metal electrically connects to the metal layer of the active circuit layer, and a surface of the conductive metal is exposed to the outside of a first surface of the silicon substrate. Therefore, a chip is able to be directly stacked on the semiconductor element without forming a passivation layer and a redistribution layer on the first surface of the silicon substrate, and the process is simplified and the manufacturing cost is decreased.

Abstract translation: 本发明涉及具有导电通孔的半导体元件及其制造方法以及具有导电通孔的半导体元件的封装。 半导体元件包括硅芯片和至少一个导电通孔。 硅芯片包括硅衬底和有源电路层。 有源电路层设置在硅衬底的第二表面上，并具有至少一个金属层。 导电通孔穿透硅衬底，并且包括导电金属。导电金属电连接到有源电路层的金属层，并且导电金属的表面暴露于硅衬底的第一表面的外部。 因此，芯片能够直接层叠在半导体元件上，而不在硅衬底的第一表面上形成钝化层和再分布层，并且简化了工艺，降低了制造成本。

公开(公告)号：US08350361B2

公开(公告)日：2013-01-08

申请号：US12830964

申请日：2010-07-06

Applicant: Chi-Tsung Chiu ,  Ying-Te Ou ,  Meng-Jen Wang

Inventor： Chi-Tsung Chiu ,  Ying-Te Ou ,  Meng-Jen Wang

IPC: H01L29/40

CPC classification number: H01L21/486 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The present invention relates to a semiconductor element having a conductive via and a method for making the same and a package having a semiconductor element with a conductive via. The semiconductor element includes a silicon chip and at least one conductive via. The silicon chip includes a silicon substrate and an active circuit layer. The active circuit layer is disposed on a second surface of the silicon substrate, and has at least one metal layer. The conductive via penetrates the silicon substrate, and includes a conductive metal. The conductive metal electrically connects to the metal layer of the active circuit layer, and a surface of the conductive metal is exposed to the outside of a first surface of the silicon substrate. Therefore, a chip is able to be directly stacked on the semiconductor element without forming a passivation layer and a redistribution layer on the first surface of the silicon substrate, and the process is simplified and the manufacturing cost is decreased.

Abstract translation: 本发明涉及具有导电通孔的半导体元件及其制造方法以及具有导电通孔的半导体元件的封装。 半导体元件包括硅芯片和至少一个导电通孔。 硅芯片包括硅衬底和有源电路层。 有源电路层设置在硅衬底的第二表面上，并具有至少一个金属层。 导电通孔穿透硅衬底，并且包括导电金属。 导电金属电连接到有源电路层的金属层，并且导电金属的表面暴露于硅衬底的第一表面的外侧。 因此，芯片能够直接层叠在半导体元件上，而不在硅衬底的第一表面上形成钝化层和再分布层，并且简化了工艺，降低了制造成本。

公开(公告)号：US08338235B2

公开(公告)日：2012-12-25

申请号：US12766549

申请日：2010-04-23

Applicant: Meng-Jen Wang

Inventor： Meng-Jen Wang

IPC: H01L21/00

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2224/81 ,  H01L2924/00

Abstract: A package process is provided. The package process includes: disposing a semiconductor substrate on a carrier, wherein the semiconductor substrate has plural contacts at a side facing the carrier; thinning the semiconductor substrate from a back side of the semiconductor substrate and then forming plural through silicon vias in the thinned semiconductor substrate; forming plural first pads on the semiconductor substrate, wherein the first pads respectively connected to the through silicon vias; bonding plural chips to the semiconductor substrate, wherein the chips are electrically connected to the corresponding pads; forming a molding compound on the semiconductor substrate to cover the chips and the first pads; separating the semiconductor substrate and the carrier and then forming plural solder balls on the semiconductor substrate; and sawing the molding compound and the semiconductor substrate.

Abstract translation: 提供包装过程。 封装工艺包括：将半导体衬底设置在载体上，其中半导体衬底在面向载体的一侧具有多个触点; 从半导体衬底的背面稀薄半导体衬底，然后在薄化的半导体衬底中形成多个通过硅通孔; 在所述半导体衬底上形成多个第一焊盘，其中所述第一焊盘分别连接到所述通孔硅通孔; 将多个芯片接合到所述半导体基板，其中所述芯片电连接到相应的焊盘; 在所述半导体衬底上形成模塑料以覆盖所述芯片和所述第一焊盘; 分离半导体衬底和载体，然后在半导体衬底上形成多个焊球; 并锯切模塑料和半导体衬底。

公开(公告)号：US20120119335A1

公开(公告)日：2012-05-17

申请号：US12945134

申请日：2010-11-12

Applicant: Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Chung-Hsi Wu ,  Meng-Jen Wang

Inventor： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Chung-Hsi Wu ,  Meng-Jen Wang

IPC: H01L29/41

CPC classification number: H01L23/544 ,  H01L23/481 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/16146

Abstract: The present invention relates to a semiconductor device with a plurality of mark through substrate vias, comprising a semiconductor substrate, a plurality of original through substrate vias and a plurality of mark through substrate vias. The original through substrate vias and the mark through substrate vias are disposed in the semiconductor substrate and protrude from the backside surface of the semiconductor substrate. The mark through substrate vias are added at a specific position and/or in a specific pattern and serve as a fiducial mark, which facilitates identifying to the position and direction on the backside surface. Thus, the redistribution layer (RDL) or the special equipment for achieving the backside alignment (BSA) is not necessary.

Abstract translation: 本发明涉及具有多个标记通过衬底通孔的半导体器件，包括半导体衬底，多个原始通过衬底通孔和多个通过衬底通孔的标记。 原始通过衬底通孔和通过衬底通孔的标记设置在半导体衬底中并从半导体衬底的背面突出。 通过基板通孔的标记在特定位置和/或特定图案中添加，并且用作基准标记，其有助于识别背面上的位置和方向。 因此，再分配层（RDL）或用于实现背侧对准（BSA）的专用设备是不必要的。