公开(公告)号：US06639946B2

公开(公告)日：2003-10-28

申请号：US09726421

申请日：2000-12-01

申请人： Miaochen Wu ,  Aria Eshraghi ,  Theodore Tewksbury

发明人： Miaochen Wu ,  Aria Eshraghi ,  Theodore Tewksbury

IPC分类号： H04B1406

CPC分类号： H04B14/06 ,  H03M3/404 ,  H03M3/43 ,  H03M3/456

摘要： A sigma delta modulation device and method for filtering high frequency intermediate frequency signals. A summing amplifier receives the analog intermediate frequency signal, and provides to a surface acoustic wave filter (SAW) an analog signal which is to be converted to a digital quantity. A quantizer digitizes the signal to produce a digitized intermediate frequency signal. A digital to analog converter provides a feedback signal from the quantizer output signal, to the summing amplifier to form a sigma delta modulation device. The SAW filter provides for high stop band attenuation of signal images within the intermediate frequency signal, and produces a low noise signal with substantially no intermodulation products.

公开(公告)号：US5691720A

公开(公告)日：1997-11-25

申请号：US613112

申请日：1996-03-08

申请人： Binan Wang ,  Timothy V. Kalthoff ,  Miaochen Wu

发明人： Binan Wang ,  Timothy V. Kalthoff ,  Miaochen Wu

IPC分类号： H03M3/02 ,  H03M3/00

CPC分类号： H03M3/392 ,  H03M3/374 ,  H03M3/43 ,  H03M3/454

摘要： Programmable resolution/bias current control circuitry is provided in a delta sigma analog-to-digital converter including an input sampling circuit, a feedback reference sampling circuit, an integrator including an operational amplifier, a comparator, and a digital filter, the input sampling circuit and the feedback reference sampling circuit being coupled to a first input of the operational amplifier, an output of the operational amplifier being coupled to an input of the comparator, an output of the comparator being coupled to an input of the digital filter. The programmable resolution/bias control circuitry includes a clock generator circuit supplying a clock signal to the input sampling circuit and the feedback sampling circuit at a sampling frequency determined by a sampling frequency control signal. A bias current generator circuit supplies a bias current to the operational amplifier to control the settling time of an output step voltage signal produced by the operational amplifier. A control circuit receives a resolution control signal and changes both the sampling frequency control signal and a bias control signal in response to the resolution control signal so as to achieve a predetermined tradeoff between resolution of the digital output and dc power dissipation of the analog-to-digital converter.

摘要翻译： 可编程分辨率/偏置电流控制电路在包括输入采样电路，反馈参考采样电路，包括运算放大器，比较器和数字滤波器的积分器的Δ-Σ模数转换器中提供，输入采样电路 并且所述反馈参考采样电路耦合到所述运算放大器的第一输入，所述运算放大器的输出耦合到所述比较器的输入，所述比较器的输出耦合到所述数字滤波器的输入端。 可编程分辨率/偏置控制电路包括以采样频率控制信号确定的采样频率向输入采样电路和反馈采样电路提供时钟信号的时钟发生器电路。 偏置电流发生器电路向运算放大器提供偏置电流以控制由运算放大器产生的输出阶跃电压信号的建立时间。 控制电路接收分辨率控制信号，并响应于分辨率控制信号改变采样频率控制信号和偏置控制信号，以便实现数字输出的分辨率与模数转换器的直流功率消耗之间的预定权衡 数字转换器

公开(公告)号：US08488657B2

公开(公告)日：2013-07-16

申请号：US12794152

申请日：2010-06-04

申请人： Miaochen Wu ,  Brian L. Dellacroce

发明人： Miaochen Wu ,  Brian L. Dellacroce

IPC分类号： H04L5/16

CPC分类号： H03L7/0807 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0025 ,  H04L7/0337

摘要： A system comprises a first circuit includes a data transmitter circuit that transmits digital data based on a first clock signal. A sync generator outputs a sync signal based on the first clock signal. A digital to analog converter circuit includes a data receiver circuit that latches the digital data based on a second clock signal. A digital to analog converter core receives an output of the data receiver circuit. A delay locked loop circuit determines a delay based on the second clock signal and the sync signal and outputs the first clock signal to the first circuit based on the second clock signal and the delay.

摘要翻译： 系统包括第一电路，其包括基于第一时钟信号发送数字数据的数据发送器电路。 同步发生器基于第一时钟信号输出同步信号。 数模转换器电路包括基于第二时钟信号锁存数字数据的数据接收器电路。 数模转换器内核接收数据接收电路的输出。 延迟锁定环电路基于第二时钟信号和同步信号确定延迟，并且基于第二时钟信号和延迟将第一时钟信号输出到第一电路。

公开(公告)号：US5703589A

公开(公告)日：1997-12-30

申请号：US611329

申请日：1996-03-08

申请人： Timothy V. Kalthoff ,  Binan Wang ,  Miaochen Wu

发明人： Timothy V. Kalthoff ,  Binan Wang ,  Miaochen Wu

IPC分类号： H03M3/02 ,  H03M1/12

CPC分类号： H03M3/34 ,  H03M3/43 ,  H03M3/456

摘要： A switched capacitor input sampling circuit in a chopper stabilized delta sigma modulator includes first and second input terminals adapted to receive a differential analog input voltage therebetween and first and second terminals coupled to first and second charge summing conductors, respectively, of the delta sigma modulator. The switched capacitor input sampling circuit also includes a first switch coupled between the first input terminal and a first conductor, a second switch coupled between the second input terminal and a second conductor, a third switch coupled between the first conductor and a bias voltage conductor, a fourth switch coupled between the second conductor and the bias voltage conductor, a first input capacitor coupled between the first conductor and a third conductor, a second input capacitor coupled between the second conductor and a fourth conductor, a fifth switch coupled between the third and fourth conductors, a sixth switch coupled between the third conductor and the first charge summing conductor, and a seventh switch coupled between the fourth conductor and the second charge summing conductor.

摘要翻译： 斩波稳定的Δ-Σ调制器中的开关电容器输入采样电路包括适于在其间接收差分模拟输入电压的第一和第二输入端，以及分别耦合到Δ-Σ调制器的第一和第二充电求和导体的第一和第二端子。 开关电容器输入采样电路还包括耦合在第一输入端和第一导体之间的第一开关，耦合在第二输入端和第二导体之间的第二开关，耦合在第一导体和偏置电压导体之间的第三开关， 耦合在所述第二导体和所述偏置电压导体之间的第四开关，耦合在所述第一导体和第三导体之间的第一输入电容器，耦合在所述第二导体和第四导体之间的第二输入电容器，耦合在所述第三导体和所述第三导体之间的第五开关， 第四导体，耦合在第三导体和第一电荷求和导体之间的第六开关，以及耦合在第四导体和第二充电求和导体之间的第七开关。

公开(公告)号：US06429797B1

公开(公告)日：2002-08-06

申请号：US09899610

申请日：2001-07-05

申请人： Miaochen Wu

发明人： Miaochen Wu

IPC分类号： H03M300

CPC分类号： H03H17/0621 ,  H03H2218/04

摘要： A bandpass delta-sigma modulator converts a signal of a nominal frequency to an oversampled digital signal. Digital decimation filter decimates the signal by multiplying the signal by first and second modulating signals. The modulating signals are selected to have a frequency which can produce a baseband signal with a nominal frequency of &pgr;*/3. By using an oversampling rate of 6 times the carrier frequency signal rate, the modulation signal of a frequency &pgr;*/3 produces a real and imaginary signal. The real and imaginary signal can be filtered in first and second filtering decimation circuits reducing the number of signal processing paths for the signal. The decimated signal is further filtered and decimated using conventional digital filtering techniques.

摘要翻译： 带通Δ-Σ调制器将标称频率的信号转换为过采样的数字信号。 数字抽取滤波器通过将信号乘以第一和第二调制信号来抽取信号。 调制信号被选择为具有可产生标称频率为pi * / 3的基带信号的频率。 通过使用载波频率信号速率的6倍的过采样率，频率pi * / 3的调制信号产生实信号和虚信号。 可以在第一和第二滤波抽取电路中对实信号和虚信号进行滤波，从而减少信号的信号处理路径的数量。 使用常规的数字滤波技术进一步对抽取的信号进行滤波和抽取。

公开(公告)号：US6037887A

公开(公告)日：2000-03-14

申请号：US611640

申请日：1996-03-06

申请人： Miaochen Wu ,  Timothy V. Kalthoff ,  Binan Wang

发明人： Miaochen Wu ,  Timothy V. Kalthoff ,  Binan Wang

IPC分类号： H03M3/02 ,  H03M3/00

CPC分类号： H03M3/486 ,  H03M3/49

摘要： A programmable gain delta sigma analog-to-digital converter includes an analog input terminal receiving an analog input voltage, a charge summing conductor, an input capacitive switching circuit, and a feedback reference capacitive switching circuit coupled to the charge summing conductor. An integrator is coupled between the charge summing conductor and a comparator which supplies a stream of digital pulses to a digital filter that produces a digital number representing the analog input voltage. The feedback reference capacitive switching circuit includes a plurality of reference sampling capacitors, selectively coupling charge between a feedback reference voltage source and an integrating capacitor of the integration in response to a programmable gain control circuit so as to provide a selected gain for the analog-to-digital converter. The sampling rate of the capacitive switching circuits is adjusted proportionally to the selected gain to improve the dynamic range of the analog-to-digital converter.

摘要翻译： 可编程增益ΔΣ模数转换器包括接收模拟输入电压的模拟输入端子，电荷求和导体，输入电容开关电路和耦合到电荷求和导体的反馈参考电容开关电路。 积分器耦合在电荷求和导体和比较器之间，比较器将数字脉冲流提供给产生代表模拟输入电压的数字数字的数字滤波器。 反馈参考电容开关电路包括多个参考采样电容器，响应于可编程增益控制电路，选择性地将反馈参考电压源和积分电容器之间的电荷耦合到一起，以便为模拟到 数字转换器 电容开关电路的采样率根据选定的增益进行调整，以改善模数转换器的动态范围。

公开(公告)号：US20110298508A1

公开(公告)日：2011-12-08

申请号：US12794152

申请日：2010-06-04

申请人： Miaochen Wu ,  Brian L. Dellacroce

发明人： Miaochen Wu ,  Brian L. Dellacroce

IPC分类号： H03L7/06

CPC分类号： H03L7/0807 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0025 ,  H04L7/0337

摘要： A system comprises a first circuit includes a data transmitter circuit that transmits digital data based on a first clock signal. A sync generator outputs a sync signal based on the first clock signal. A digital to analog converter circuit includes a data receiver circuit that latches the digital data based on a second clock signal. A digital to analog converter core receives an output of the data receiver circuit. A delay locked loop circuit determines a delay based on the second clock signal and the sync signal and outputs the first clock signal to the first circuit based on the second clock signal and the delay.

摘要翻译： 系统包括第一电路，其包括基于第一时钟信号发送数字数据的数据发送器电路。 同步发生器基于第一时钟信号输出同步信号。 数模转换器电路包括基于第二时钟信号锁存数字数据的数据接收器电路。 数模转换器内核接收数据接收电路的输出。 延迟锁定环电路基于第二时钟信号和同步信号确定延迟，并且基于第二时钟信号和延迟将第一时钟信号输出到第一电路。

公开(公告)号：US06373316B1

公开(公告)日：2002-04-16

申请号：US09484358

申请日：2000-01-18

申请人： Miaochen Wu

发明人： Miaochen Wu

IPC分类号： G06F744

CPC分类号： G06F7/548 ,  G06F7/4812

摘要： By sampling at six times the carrier frequency cosine and sine multiplication circuits are found to be constructable from simple shift and inversion circuit. Shifting and inversion are controlled by means of a simple finite state machine or other circuits cycling through a six cycle periodic sequence.

摘要翻译： 通过采样六次，发现载波频率余弦和正弦乘法电路可以从简单的移位和反相电路构造。 移位和反转通过简单的有限状态机或循环通过六周期周期序列的其他电路来控制。