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公开(公告)号：US08823567B2
公开(公告)日：2014-09-02
申请号：US13534716
申请日：2012-06-27
申请人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
发明人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
CPC分类号： H03H11/04 , H03H2011/0488 , H03M3/404
摘要： Two T filters, one of which includes two resistive elements and one capacitive element and the other of which includes two capacitive elements and one resistive element, are inserted in a negative-feedback section of an operational amplifier, and a resistive element and a capacitive element are connected between each of intermediate nodes and a signal input terminal. A resistive element and a capacitive element which are connected to each other in parallel are connected between the signal input terminal and an inverting input terminal of the operational amplifier. With this configuration, overall admittances where elements connected to the corresponding intermediate nodes are in parallel connection are equal to each other.
摘要翻译： 两个T滤波器，其中一个包括两个电阻元件和一个电容元件，另一个包括两个电容元件和一个电阻元件，插入到运算放大器的负反馈部分中，电阻元件和电容元件 连接在每个中间节点和信号输入端子之间。 并联连接的电阻元件和电容元件连接在信号输入端子和运算放大器的反相输入端子之间。 利用这种配置，连接到对应的中间节点的元件并联连接的整体导纳彼此相等。
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公开(公告)号：US20110169677A1
公开(公告)日：2011-07-14
申请号：US13073335
申请日：2011-03-28
申请人： Shiro DOSHO , Kazuo Matsukawa , Yosuke Mitani
发明人： Shiro DOSHO , Kazuo Matsukawa , Yosuke Mitani
CPC分类号： H03M3/454 , H03H11/1252 , H03M3/404 , H03M3/438
摘要： Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.
摘要翻译： 两个电阻元件和电容元件耦合在运算放大器的第一节点和反相输入端子，运算放大器的输出端子和公共节点之间。 电阻元件和电容元件耦合在第一节点和信号输入端子之间。 两个电容元件和电阻元件耦合在第二节点和反相输入端子，输出端子和公共节点之间。 两个电容元件耦合在第二节点和每个信号输入端和公共节点之间。
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3.发明授权Programmable dynamic range receiver with adjustable dynamic range analog to digital converter 失效可编程动态范围接收器，具有可调动态范围的模数转换器
公开(公告)号：US6134430A
公开(公告)日：2000-10-17
申请号：US987853
申请日：1997-12-09
CPC分类号： H04B1/1027 , H03M3/488 , H04B1/109 , H03M3/404 , H03M3/414
摘要： A programmable dynamic range receiver which provides the requisite level of performance at reduced power consumption. The .SIGMA..DELTA. ADC within the receiver is designed with one or more loops. Each loop provides a predetermined dynamic range performance. The loops can be enabled or disabled based on the required dynamic range and a set of dynamic range thresholds. The .SIGMA..DELTA. ADC is also designed with adjustable bias current. The dynamic range of the .SIGMA..DELTA. ADC varies approximately proportional to the bias current. By adjusting the bias current, the required dynamic range can be provided by the .SIGMA..DELTA. ADC with minimal power consumption. A reference voltage of the .SIGMA..DELTA. ADC can be descreased when high dynamic range is not required, thereby allowing for less bias current in the .SIGMA..DELTA. ADC and supporting circuitry. The dynamic range of the .SIGMA..DELTA. ADC is a also function of the oversampling ratio which is proportional to the sampling frequency. High dynamic range requires a high oversampling ratio. When high dynamic range is not required, the sampling frequency can be lowered.
摘要翻译： 可编程动态范围接收器，以降低功耗提供必要的性能水平。 接收机内的SIGMA DELTA ADC设计有一个或多个回路。 每个循环提供预定的动态范围性能。 可以根据所需的动态范围和一组动态范围阈值启用或禁用这些循环。 SIGMA DELTA ADC还设计有可调偏置电流。 SIGMA DELTA ADC的动态范围与偏置电流大致成正比。 通过调整偏置电流，所需的动态范围可由SIGMA DELTA ADC提供，功耗最小。 当不需要高动态范围时，可以降低SIGMA DELTA ADC的参考电压，从而在SIGMA DELTA ADC和支持电路中允许更少的偏置电流。 SIGMA DELTA ADC的动态范围也是与采样频率成比例的过采样比的函数。 高动态范围需要高过采样比。 当不需要高动态范围时，可以降低采样频率。
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公开(公告)号：US5841822A
公开(公告)日：1998-11-24
申请号：US982179
申请日：1997-12-01
CPC分类号： H03H19/004 , H03M3/404 , H03M3/43 , H03M3/454
摘要： A communication receiver (600) utilizes a band-pass sigma-delta converter (100) for receiving a radio signal. The band-pass sigma-delta converter (100) includes a comparator (106) coupled to an adder-filter (101) for making a comparison between a predetermined reference level (110) and an intermediate signal (125), and for generating a comparison result signal (114) responsive to the comparison. A storage element (108) is used for storing the comparison result signal (114) for a predetermined delay period, thereby producing a clocked output signal (118). The adder-filter (101) is coupled to an analog signal (103) and to the clocked output signal (118) for subtracting the clocked output signal (118) from the analog signal (103) to produce a difference signal (120) that is filtered by a commutating filter (400) for generating the intermediate signal (125) responsive to the difference signal (120).
摘要翻译： 通信接收机（600）利用带通Σ-Δ转换器（100）来接收无线电信号。 带通Σ-Δ转换器（100）包括耦合到加法器滤波器（101）的比较器（106），用于在预定参考电平（110）和中间信号（125）之间进行比较，并且用于产生 比较结果信号（114）响应于比较。 存储元件（108）用于在预定的延迟周期内存储比较结果信号（114），从而产生时钟输出信号（118）。 加法器滤波器（101）耦合到模拟信号（103）和时钟输出信号（118），用于从模拟信号（103）中减去时钟输出信号（118）以产生差分信号（120），其中， 通过换向滤波器（400）进行滤波，用于响应差分信号（120）产生中间信号（125）。
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公开(公告)号：US5608400A
公开(公告)日：1997-03-04
申请号：US519593
申请日：1995-08-24
申请人： Leopold E. Pellon
发明人： Leopold E. Pellon
摘要： A sigma-delta analog-to-digital converter (10) provides high loop gain for suppression of noise components by use of a regenerative feedback loop or resonator (50), which produces a comb resonance response 212), embedded in the main degenerative feedback loop (48). The main loop includes an ADC (32) which samples at a clock frequency, which in turn defines a Nyquist frequency. The main loop also includes a DAC (38) which has a transfer function (42), which is equalized by a filter (44). The resonator (50) includes a low-pass filter (52) which matches the equalized main loop transfer function, a DC block (56), and a null filter (54) which nulls the resonator gain at the comb peak which lies above the Nyquist frequency. The open-loop transfer function of the regenerative loop (50) is set to unity gain and 0.degree..+-.N 360.degree. phase at the frequency of the analog input signal. A multipole embodiment (510) has multiple regenerative loops (55o) which produce multipole noise rejection (642). Resonators (751) are used in other .SIGMA..DELTA. ADCs (790, 890).
摘要翻译： Σ-Δ模数转换器（10）通过使用嵌入在主退化反馈中的再生反馈回路或共振器（50）提供用于抑制噪声分量的高环路增益，其产生梳状共振响应212） 循环（48）。 主回路包括ADC（32），其以时钟频率进行采样，其又限定奈奎斯特频率。 主回路还包括具有传递函数（42）的DAC（38），其由滤波器（44）均衡。 谐振器（50）包括与均衡的主环路传递函数相匹配的低通滤波器（52），DC块（56）和零滤波器（54），其使位于 奈奎斯特频率 再生回路（50）的开环传递函数设定为模数输入信号频率下的单位增益和0°+/- N 360°相位。 多极实施例（510）具有产生多极噪声抑制的多个再生回路（55o）（642）。 谐振器（751）用于其他SIGMA DELTA ADC（790,890）。
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公开(公告)号：US5523719A
公开(公告)日：1996-06-04
申请号：US196328
申请日：1994-02-15
申请人： Lorenzo L. Longo , Raouf Halim , Bor-Rong Horng
发明人： Lorenzo L. Longo , Raouf Halim , Bor-Rong Horng
CPC分类号： H03M3/404 , H03H19/004 , H03M3/458
摘要： A digitally driven, analog bandpass filter has an analog summer and two analog delay elements connected in a loop. An input signal to the filter is applied to a plus input terminal of the summer, and the output of the second delay elements is applied to a minus input terminal of the summer. The output of filter may be taken either from the output of the summer, or from the output of the second delay element, or from any point in between. Each delay element is driven by a two phase non-overlapping clock, and each element passes a charge from a first capacitor through an op amp to either a second capacitor (first phase) or a third capacitor (second phase). Amplification may be provided by adjusting the ratio of the second (or third) capacitor to the first capacitor. If a differential op amp is used, both sides of the op amp are clocked together, and each side has its own trio of capacitors identical to the trio on the other side. The passband is centered precisely on one-quarter of the clock frequency, and does not vary with manufacturing variances in the components of the filter.
摘要翻译： 数字驱动的模拟带通滤波器具有模拟加法器和连接在一个回路中的两个模拟延迟元件。 将滤波器的输入信号施加到加法器的正输入端，并且将第二延迟元件的输出施加到夏季的负输入端。 滤波器的输出可以从夏季的输出，或从第二延迟元件的输出，或者从中间的任何点获取。 每个延迟元件由两相非重叠时钟驱动，并且每个元件将来自第一电容器的电荷通过运算放大器传递到第二电容器（第一相位）或第三电容器（第二相位）。 可以通过调节第二（或第三）电容器与第一电容器的比率来提供放大。 如果使用差分运算放大器，则运算放大器的两侧都在一起计时，并且每一侧都有三个与三端三端相同的三相电容。 通带中心精确地位于时钟频率的四分之一，并且不随过滤器组件的制造差异而变化。
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公开(公告)号：US20180034471A1
公开(公告)日：2018-02-01
申请号：US15659170
申请日：2017-07-25
发明人： Arnaud VERDANT , William GUICQUERO
IPC分类号： H03M3/00
摘要： A sigma-delta converter including a sigma-delta modulator including at least one analog filter capable, for each cycle of a conversion phase, of receiving an internal analog signal originating from the analog input signal and of supplying an analog output signal, wherein: the contribution of the internal analog signal to the output value of the filter is smaller at a given cycle of the conversion phase than at a previous cycle, the contributions to the different cycles being governed by a first predetermined law which is a function of the rank of the cycle; and the duration of a given cycle of the conversion phase is shorter than the duration of a previous cycle, the durations of the different cycles being governed by a second predetermined law which is a function of the rank of the cycle in the conversion phase.
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公开(公告)号：US09621175B2
公开(公告)日：2017-04-11
申请号：US15251689
申请日：2016-08-30
摘要： Provided are, among other things, systems, apparatuses, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. One such apparatus includes an input line for accepting an input signal that is continuous in time and continuously variable, multiple processing branches coupled to the input line, and an adder coupled to outputs of the processing branches, with each of the processing branches including a bandpass noise-shaping circuit, a sampling/quantization circuit coupled to an output of the bandpass noise-shaping circuit, a digital bandpass filter coupled to an output of the sampling/quantization circuit, and a line coupling an output of the sampling/quantization converter circuit back into the bandpass noise-shaping circuit. A center frequency of the digital bandpass filter in each processing branch corresponds to a stopband region in a quantization noise transfer function for the bandpass noise-shaping circuit in the same processing branch.
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9.发明授权Communication unit, digital band-pass sigma-delta modulator and method therefor 有权通信单元，数字带通Σ-Δ调制器及其方法公开(公告)号：US09166617B1
公开(公告)日：2015-10-20
申请号：US14574568
申请日：2014-12-18
CPC分类号： H03M3/404 , H03G3/3042 , H03K7/08 , H03M3/30 , H03M3/402 , H03M3/502 , H03M7/3017 , H04L27/2092 , H04L27/368
摘要： A communication unit comprises a power DAC. The DAC comprises: a switched mode power amplifier (SMPA); and a digital band-pass sigma-delta modulator operably coupled to the SMPA. The sigma-delta modulator comprises an input to receive an input baseband signal; a delay; an adder module arranged to add a feedback signal with an output from the delay; and at least two feedback branches. The sigma-delta modulator is arranged to digitally oversample the input baseband signal such that a ratio of a sampling frequency employed by the sigma-delta modulator to a radio frequency (RF) output from the DAC is fixed and the sampling frequency tuned or wherein the sampling frequency is fixed and the ratio is adjusted, such that a first feedback branch in the sigma-delta modulator is formed using at least one from a group of: a zero gain, an additive inverse of a second feedback branch.
摘要翻译： 通信单元包括功率DAC。 DAC包括：开关模式功率放大器（SMPA）; 以及可操作地耦合到SMPA的数字带通Σ-Δ调制器。 Σ-Δ调制器包括用于接收输入基带信号的输入端; 延迟; 加法器模块，被布置成将反馈信号与来自所述延迟的输出相加; 和至少两个反馈分支。 Σ-Δ调制器被布置为对输入基带信号进行数字过采样，使得由Σ-Δ调制器采用的采样频率与DAC输出的射频（RF）的比率是固定的，并且采样频率调谐或其中 采样频率是固定的并且比率被调整，使得使用来自以下的组中的至少一个来形成Σ-Δ调制器中的第一反馈支路：零增益，第二反馈支路的加法逆。
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10.发明申请COMMUNICATION UNIT, DIGITAL BAND-PASS SIGMA-DELTA MODULATOR AND METHOD THEREFOR 有权通信单元，数字带通信号调制器及其方法公开(公告)号：US20150280732A1
公开(公告)日：2015-10-01
申请号：US14574568
申请日：2014-12-18
IPC分类号： H03M3/00
CPC分类号： H03M3/404 , H03G3/3042 , H03K7/08 , H03M3/30 , H03M3/402 , H03M3/502 , H03M7/3017 , H04L27/2092 , H04L27/368
摘要： A communication unit comprises a power DAC. The DAC comprises: a switched mode power amplifier (SMPA); and a digital band-pass sigma-delta modulator operably coupled to the SMPA. The sigma-delta modulator comprises an input to receive an input baseband signal; a delay; an adder module arranged to add a feedback signal with an output from the delay; and at least two feedback branches. The sigma-delta modulator is arranged to digitally oversample the input baseband signal such that a ratio of a sampling frequency employed by the sigma-delta modulator to a radio frequency (RF) output from the DAC is fixed and the sampling frequency tuned or wherein the sampling frequency is fixed and the ratio is adjusted, such that a first feedback branch in the sigma-delta modulator is formed using at least one from a group of: a zero gain, an additive inverse of a second feedback branch.
摘要翻译： 通信单元包括功率DAC。 DAC包括：开关模式功率放大器（SMPA）; 以及可操作地耦合到SMPA的数字带通Σ-Δ调制器。 Σ-Δ调制器包括用于接收输入基带信号的输入端; 延迟; 加法器模块，被布置成将反馈信号与来自所述延迟的输出相加; 和至少两个反馈分支。 Σ-Δ调制器被布置为对输入基带信号进行数字过采样，使得由Σ-Δ调制器采用的采样频率与DAC输出的射频（RF）的比率是固定的，并且采样频率调谐或其中 采样频率是固定的并且比率被调整，使得使用来自以下的组中的至少一个来形成Σ-Δ调制器中的第一反馈支路：零增益，第二反馈支路的加法逆。
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