公开(公告)号：US5597767A

公开(公告)日：1997-01-28

申请号：US369838

申请日：1995-01-06

申请人： Michael A. Mignardi ,  Laurinda Ng ,  Ronald S. Croff ,  Robert McKenna ,  Lawrence D. Dyer

发明人： Michael A. Mignardi ,  Laurinda Ng ,  Ronald S. Croff ,  Robert McKenna ,  Lawrence D. Dyer

IPC分类号： B81C1/00 ,  H01L21/301 ,  H01L21/78 ,  H01L21/302

CPC分类号： B81C1/00873 ,  H01L21/78 ,  B81C2201/053 ,  Y10S148/012 ,  Y10S148/028

摘要： A method of separating wafers, such as those used for semiconductor device manufacture, into die. A partly fabricated wafer is covered with a protective coating over its top surface (10). The wafer is then inscribed to define separation lines between die, with the separation lines being of a predetermined depth (12). The protective coating is then removed (14), and at least one processing step is performed at the wafer level (15, 22-24), before the inscribed wafer is separated into die. Then, the wafer is separated into die along the separation lines (17).

摘要翻译： 将诸如用于半导体器件制造的晶片的晶片分离成芯片的方法。 部分制造的晶片在其顶表面（10）上被覆盖有保护涂层。 然后将晶片刻上以限定管芯之间的分隔线，分离线具有预定深度（12）。 然后去除保护涂层（14），并且在将内切晶片分离成模具之前，在晶片级（15,22-24）处执行至少一个处理步骤。 然后，将晶片沿分离线（17）分离成模具。

公开(公告)号：US20050127516A1

公开(公告)日：2005-06-16

申请号：US10735374

申请日：2003-12-12

申请人： Betty Mercer ,  Alec Morton ,  Byron Williams ,  Laurinda Ng ,  C. Thompson ,  Der-E Jan ,  Sunny Lee ,  Phuong-Lan Thi Tran

发明人： Betty Mercer ,  Alec Morton ,  Byron Williams ,  Laurinda Ng ,  C. Thompson ,  Der-E Jan ,  Sunny Lee ,  Phuong-Lan Thi Tran

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L29/40

CPC分类号： H01L21/76877 ,  H01L21/76838

摘要： The present invention relates to integrated circuits comprising a protective overcoat and thick copper connectors. According to one aspect of the inventions, vias in the protective overcoat are substantially filled with tungsten plugs, or plugs of another metal with a relatively low coefficient of thermal expansion. According to another aspect of the invention, large vias in the protective overcoat are replaced with arrays of smaller vias. The invention reduces the likelihood of device failures during temperature cycling tests. Also, the invention allows for smaller vias in the protective overcoat and removal of interconnect functions to the thick copper layer.

摘要翻译： 本发明涉及包括保护外涂层和厚铜连接器的集成电路。 根据本发明的一个方面，保护性外涂层中的通孔基本上填充有钨塞或具有相对低的热膨胀系数的另一种金属的塞子。 根据本发明的另一方面，保护性外涂层中的大的通孔被更小的通孔的阵列所取代。 本发明降低了温度循环测试期间设备故障的可能性。 此外，本发明允许保护性外涂层中的较小的通孔和去除厚铜层的互连功能。

公开(公告)号：US20050239277A1

公开(公告)日：2005-10-27

申请号：US10828592

申请日：2004-04-21

申请人： Betty Mercer ,  Erika Shoemaker ,  Byron Williams ,  Laurinda Ng ,  Alec Morton ,  C. Thompson

发明人： Betty Mercer ,  Erika Shoemaker ,  Byron Williams ,  Laurinda Ng ,  Alec Morton ,  C. Thompson

IPC分类号： G03C1/85 ,  H01L21/44 ,  H01L21/60

CPC分类号： H01L24/11 ,  H01L2224/039 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

摘要： The present invention provides an interconnect for use in an integrated circuit, a method for manufacturing the interconnect, and a method for manufacturing an integrated circuit including the interconnect. The interconnect (100), among other elements, includes a surface conductive lead (160) located in an opening formed within a protective overcoat (110), and a barrier layer (140) located between the protective overcoat (110) and the surface conductive lead (160), a portion of the barrier layer (140) forming a skirt (145) that extends outside a footprint of the surface conductive lead (160).

摘要翻译： 本发明提供了一种用于集成电路的互连，一种用于制造该互连的方法，以及一种用于制造包括该互连的集成电路的方法。 除了其它元件之外，互连（100）包括位于形成在保护外涂层（110）内的开口中的表面导电引线（160）和位于保护外涂层（110）和表面导电 导线（160），阻挡层（140）的形成裙部（145）的部分延伸到表面导电引线（160）的覆盖区外部。

公开(公告)号：US20070075348A1

公开(公告)日：2007-04-05

申请号：US11239244

申请日：2005-09-30

申请人： Byron Williams ,  Maxwell Lippitt ,  Darius Crenshaw ,  Laurinda Ng ,  Betty Mercer ,  Scott Montgomery ,  C. Thompson

发明人： Byron Williams ,  Maxwell Lippitt ,  Darius Crenshaw ,  Laurinda Ng ,  Betty Mercer ,  Scott Montgomery ,  C. Thompson

IPC分类号： H01L29/94 ,  H01L21/8242

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： In accordance with the invention, there are methods for making and there is an integrated circuit comprising a semiconductor substrate comprising device elements and a metallization layer interconnecting the device elements and having an uppermost layer. The integrated circuit can also include a protective overcoat formed over the metallization layer, the protective overcoat having a plurality of patterned regions that expose portions of the metallization layer, a first conductive layer formed on the protective overcoat, and a dielectric layer formed over the first conductive layer. The integrated circuit can further include a second conductive layer formed over the dielectric layer and a plurality of sidewall spacers contacting end portions of the first conductive layer.

摘要翻译： 根据本发明，存在制造方法，并且存在包括半导体衬底的集成电路，该半导体衬底包括器件元件和互连器件元件并具有最上层的金属化层。 集成电路还可以包括形成在金属化层上的保护外涂层，保护外涂层具有暴露金属化层的部分的多个图案化区域，形成在保护外涂层上的第一导电层，以及形成在第一 导电层。 集成电路还可以包括形成在电介质层上的第二导电层和与第一导电层的端部接触的多个侧壁间隔件。