-
1.发明授权Method and apparatus improving gate oxide reliability by controlling accumulated charge 有权通过控制累积电荷提高栅极氧化可靠性的方法和装置公开(公告)号：US07890891B2
公开(公告)日：2011-02-15
申请号：US11520912
申请日：2006-09-14
申请人： Michael A. Stuber , Christopher N. Brindle , Dylan J. Kelly , Clint L. Kemerling , George P. Imthurn , Robert B. Welstand , Mark L. Burgener , Alexander Dribinsky , Tae Youn Kim
发明人： Michael A. Stuber , Christopher N. Brindle , Dylan J. Kelly , Clint L. Kemerling , George P. Imthurn , Robert B. Welstand , Mark L. Burgener , Alexander Dribinsky , Tae Youn Kim
IPC分类号： G06F17/50
CPC分类号： H01L29/78615 , H01L27/1203 , H01L29/4908 , H01L29/78651 , H01L29/78654 , H01L29/78657 , H03K17/162
摘要： A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.
摘要翻译： 公开了一种用于使用累积电荷控制（ACC）技术来改善绝缘体上半导体（SOI）金属氧化物 - 硅场效应晶体管（MOSFET）器件的栅极氧化可靠性的方法和装置。 该方法和装置适于去除，减少或以其他方式控制SOI MOSFET中的累积电荷，从而产生FET性能特性的改进。 在一个实施例中，电路包括以累积电荷状态运行的MOSFET，以及用于控制可操作地耦合到SOI MOSFET的累积电荷的装置。 首先确定不受控制的累积电荷对SOI MOSFET的栅极氧化物的时间依赖介电击穿（TDDB）的影响。 第二次确定SOI MOSFET的栅极氧化物的受控累积电荷对TDDB的影响。 SOI MOSFET适于具有响应于第一和第二确定的选择的平均时间分辨率，并且使用用于可操作地耦合到SOI MOSFET的累积电荷控制的技术来操作电路。 在一个实施例中，累积的电荷控制技术包括使用可操作地耦合到SOI MOSFET体的累积电荷宿。
-
2.发明授权Method and apparatus improving gate oxide reliability by controlling accumulated charge 有权通过控制累积电荷提高栅极氧化可靠性的方法和装置公开(公告)号：US08954902B2
公开(公告)日：2015-02-10
申请号：US13028144
申请日：2011-02-15
申请人： Michael A. Stuber , Christopher N. Brindle , Dylan J. Kelly , Clint L. Kemerling , George P. Imthurn , Mark L. Burgener , Alexander Dribinsky , Tae Youn Kim
发明人： Michael A. Stuber , Christopher N. Brindle , Dylan J. Kelly , Clint L. Kemerling , George P. Imthurn , Mark L. Burgener , Alexander Dribinsky , Tae Youn Kim
IPC分类号： G06F17/50 , H03K17/16 , H01L27/12 , H01L29/49 , H01L29/786
CPC分类号： H01L29/78615 , H01L27/1203 , H01L29/4908 , H01L29/78651 , H01L29/78654 , H01L29/78657 , H03K17/162
摘要： A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.
摘要翻译： 公开了一种用于使用累积电荷控制（ACC）技术来改善绝缘体上半导体（SOI）金属氧化物 - 硅场效应晶体管（MOSFET）器件的栅极氧化可靠性的方法和装置。 该方法和装置适于去除，减少或以其他方式控制SOI MOSFET中的累积电荷，从而产生FET性能特性的改进。 在一个实施例中，电路包括以累积电荷状态运行的MOSFET，以及用于控制可操作地耦合到SOI MOSFET的累积电荷的装置。 首先确定不受控制的累积电荷对SOI MOSFET的栅极氧化物的时间依赖介电击穿（TDDB）的影响。 第二次确定SOI MOSFET的栅极氧化物的受控累积电荷对TDDB的影响。 SOI MOSFET适于具有响应于第一和第二确定的选择的平均时间分辨率，并且使用用于可操作地耦合到SOI MOSFET的累积电荷控制的技术来操作电路。 在一个实施例中，累积的电荷控制技术包括使用可操作地耦合到SOI MOSFET体的累积电荷宿。
-
3.发明申请Method and Apparatus Improving Gate Oxide Reliability by Controlling Accumulated Charge 有权方法和装置通过控制累积电荷来提高栅氧化物的可靠性公开(公告)号：US20110227637A1
公开(公告)日：2011-09-22
申请号：US13028144
申请日：2011-02-15
申请人： Michael A. Stuber , Christopher N. Brindle , Dylan J. Kelly , Clint L. Kemerling , George P. Imthurn , Mark L. Burgener , Alexander Dribinsky , Tae Youn Kim
发明人： Michael A. Stuber , Christopher N. Brindle , Dylan J. Kelly , Clint L. Kemerling , George P. Imthurn , Mark L. Burgener , Alexander Dribinsky , Tae Youn Kim
IPC分类号： G05F1/10 , H01L29/772
CPC分类号： H01L29/78615 , H01L27/1203 , H01L29/4908 , H01L29/78651 , H01L29/78654 , H01L29/78657 , H03K17/162
摘要： A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.
摘要翻译： 公开了一种用于使用累积电荷控制（ACC）技术来改善绝缘体上半导体（SOI）金属氧化物 - 硅场效应晶体管（MOSFET）器件的栅极氧化可靠性的方法和装置。 该方法和装置适于去除，减少或以其他方式控制SOI MOSFET中的累积电荷，从而产生FET性能特性的改进。 在一个实施例中，电路包括以累积电荷状态运行的MOSFET，以及用于控制可操作地耦合到SOI MOSFET的累积电荷的装置。 首先确定不受控制的累积电荷对SOI MOSFET的栅极氧化物的时间依赖介电击穿（TDDB）的影响。 第二次确定SOI MOSFET的栅极氧化物的受控累积电荷对TDDB的影响。 SOI MOSFET适于具有响应于第一和第二确定的选择的平均时间分辨率，并且使用用于可操作地耦合到SOI MOSFET的累积电荷控制的技术来操作电路。 在一个实施例中，累积的电荷控制技术包括使用可操作地耦合到SOI MOSFET体的累积电荷宿。
-
公开(公告)号：US08143935B2
公开(公告)日：2012-03-27
申请号：US11881816
申请日：2007-07-26
IPC分类号： H03K17/00
摘要： A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.
-
公开(公告)号：US08174303B2
公开(公告)日：2012-05-08
申请号：US12460442
申请日：2009-07-17
IPC分类号： H03L5/00
摘要： A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.
-
公开(公告)号：US20110156819A1
公开(公告)日：2011-06-30
申请号：US13054781
申请日：2009-07-17
CPC分类号： H03F1/26 , H02M3/07 , H03F3/45183 , H03F3/45237 , H03F3/45475 , H03F3/45659 , H03F2200/453 , H03F2200/456 , H03F2200/474 , H03F2203/45138 , H03F2203/45188 , H03F2203/45366 , H03F2203/45418 , H03F2203/45424 , H03F2203/45471 , H03F2203/45642 , H03H11/245 , H03K17/145
摘要： A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and/or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A charge pump for the bias generation may include a regulating feed back loop including an OTA that is also suitable for other uses, the OTA having a ratio-control input that controls a current mirror ratio in a differential amplifier over a continuous range, and optionally has differential outputs including an inverting output produced by a second differential amplifier that optionally includes a variable ratio current mirror controlled by the same ratio-control input. The ratio-control input may therefore control a common mode voltage of the differential outputs of the OTA. A control loop around the OTA may be configured to control the ratio of one or more variable ratio current mirrors, which may particularly control the output common mode voltage, and may control it such that the inverting output level tracks the non-inverting output level to cause the amplifier to function as a high-gain integrator.
-
公开(公告)号：US09030248B2
公开(公告)日：2015-05-12
申请号：US12460442
申请日：2009-07-17
IPC分类号： H03L5/00 , H03K19/0185 , H03K19/003
CPC分类号： H03K19/0185 , H03K19/00369
摘要： A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.
摘要翻译： 电平移位器或方法产生由提供VDD或公共端的高端源极驱动器提供的驱动器的最终输出，以及提供通用或VSS的低端源极驱动器。 引入延迟以防止源驱动器从共同开始向供应轨转换，直到轨道上的延迟源驱动器开始朝向普通转换。 电平移位器可以是单端或差分，并且延迟源驱动器可以与延迟源驱动器耦合到相同的最终输出驱动器，或者可以耦合到不同的最终输出驱动器。 电平移位器可以具有第二电平移位器前端级，其可以具有由电容器耦合的高侧和低侧中间源驱动器输出，和/或可以经由公共阻抗将所述电源中的一个耦合到所有中间源驱动器 或当前极限Zs。
-
公开(公告)号：US08994452B2
公开(公告)日：2015-03-31
申请号：US13054781
申请日：2009-07-17
CPC分类号： H03F1/26 , H02M3/07 , H03F3/45183 , H03F3/45237 , H03F3/45475 , H03F3/45659 , H03F2200/453 , H03F2200/456 , H03F2200/474 , H03F2203/45138 , H03F2203/45188 , H03F2203/45366 , H03F2203/45418 , H03F2203/45424 , H03F2203/45471 , H03F2203/45642 , H03H11/245 , H03K17/145
摘要： A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and/or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A charge pump for the bias generation may include a regulating feedback loop including an OTA that is also suitable for other uses, the OTA having a ratio-control input that controls a current mirror ratio in a differential amplifier over a continuous range, and optionally has differential outputs including an inverting output produced by a second differential amplifier that optionally includes a variable ratio current mirror controlled by the same ratio-control input. The ratio-control input may therefore control a common mode voltage of the differential outputs of the OTA. A control loop around the OTA may be configured to control the ratio of one or more variable ratio current mirrors, which may particularly control the output common mode voltage, and may control it such that the inverting output level tracks the non-inverting output level to cause the amplifier to function as a high-gain integrator.
-
公开(公告)号：US20100033226A1
公开(公告)日：2010-02-11
申请号：US12460442
申请日：2009-07-17
IPC分类号： H03L5/00
CPC分类号： H03K19/0185 , H03K19/00369
摘要： A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.
摘要翻译： 电平移位器或方法产生由提供VDD或公共端的高端源极驱动器提供的驱动器的最终输出，以及提供通用或VSS的低端源极驱动器。 引入延迟以防止源驱动器从共同开始向供应轨转换，直到轨道上的延迟源驱动器开始朝向普通转换。 电平移位器可以是单端或差分，并且延迟源驱动器可以与延迟源驱动器耦合到相同的最终输出驱动器，或者可以耦合到不同的最终输出驱动器。 电平移位器可以具有第二电平移位器前端级，其可以具有由电容器耦合的高侧和低侧中间源极驱动器输出，和/或可以通过公共阻抗将所述电源中的一个耦合到所有中间源驱动器 或当前极限Zs。
-
公开(公告)号：US20120038344A1
公开(公告)日：2012-02-16
申请号：US13016875
申请日：2011-01-28
IPC分类号： G05F3/02
摘要： Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.
摘要翻译： 本文一般地描述信号偏置发生器和调节器的实施例。 可以描述和要求保护其他实施例。
-
-
-
-
-
-
-
-
-
搜索结果
18 条记录 (耗时 0.044 秒)