公开(公告)号：US08466054B2

公开(公告)日：2013-06-18

申请号：US13311454

申请日：2011-12-05

Applicant: Michael A. Stuber ,  Chris Brindle ,  Stuart B. Molin

Inventor： Michael A. Stuber ,  Chris Brindle ,  Stuart B. Molin

IPC: H01L21/44

CPC classification number: H01L23/3677 ,  H01L23/36 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A thermal path is formed in a layer transferred semiconductor structure. The layer transferred semiconductor structure has a semiconductor wafer and a handle wafer bonded to a top side of the semiconductor wafer. The semiconductor wafer has an active device layer formed therein. The thermal path is in contact with the active device layer within the semiconductor wafer. In some embodiments, the thermal path extends from the active device layer to a substrate layer of the handle wafer. In some embodiments, the thermal path extends from the active device layer to a back side external thermal contact below the active device layer.

Abstract translation: 热转移路径形成在层转移的半导体结构中。 层转移的半导体结构具有半导体晶片和结合到半导体晶片的顶侧的处理晶片。 半导体晶片在其中形成有源器件层。 热路径与半导体晶片内的有源器件层接触。 在一些实施例中，热路径从有源器件层延伸到处理晶片的衬底层。 在一些实施例中，热路径从有源器件层延伸到有源器件层下面的后侧外部热接触。

公开(公告)号：US07524710B2

公开(公告)日：2009-04-28

申请号：US12134681

申请日：2008-06-06

Applicant: Anthony M. Miscione ,  George Imthurn ,  Eugene F. Lyons ,  Michael A. Stuber

Inventor： Anthony M. Miscione ,  George Imthurn ,  Eugene F. Lyons ,  Michael A. Stuber

IPC: H01L27/01

CPC classification number: H01L27/1203 ,  H01L21/86 ,  H01L27/12

Abstract: A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer.

Abstract translation: 一种绝缘体上的金属氧化物半导体器件，包括：超蓝宝石蓝宝石衬底; 形成在所述超薄硅层中的至少一个P沟道MOS晶体管; 和N型杂质注入到超薄硅层和蓝宝石衬底内，使得蓝宝石层中的N型杂质浓度高于超薄硅层中的杂质浓度峰值。

公开(公告)号：US08357975B2

公开(公告)日：2013-01-22

申请号：US13459110

申请日：2012-04-28

Applicant: Michael A. Stuber ,  Stuart B. Molin ,  Paul A. Nygaard

Inventor： Michael A. Stuber ,  Stuart B. Molin ,  Paul A. Nygaard

IPC: H01L27/01

CPC classification number: H01L27/1207 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

Abstract: Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.

Abstract translation: 本发明的实施例提供从绝缘体上半导体（SOI）结构中的有源器件的主体去除过量载流子。 在一个实施例中，公开了一种制造集成电路的方法。 在一个步骤中，有源器件形成在绝缘体上半导体晶片的有源层中。 在另一步骤中，从设置在SOI晶片的背面的衬底层去除衬底材料。 在另一步骤中，从SOI晶片的背面去除绝缘体材料以形成挖掘的绝缘体区域。 在另一个步骤中，导电层沉积在挖掘的绝缘体区域上。 沉积导电层使其与挖掘的绝缘体区域的第一部分中的有源器件的主体物理接触。 导电层然后将本体连接到挖掘的绝缘体区域的第二分离部分中的触点。

公开(公告)号：US20120211835A1

公开(公告)日：2012-08-23

申请号：US13459110

申请日：2012-04-28

Applicant: Michael A. Stuber ,  Stuart B. Molin ,  Paul A. Nygaard

Inventor： Michael A. Stuber ,  Stuart B. Molin ,  Paul A. Nygaard

IPC: H01L29/772 ,  H01L21/283

CPC classification number: H01L27/1207 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

Abstract: Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.

Abstract translation: 本发明的实施例提供从绝缘体上半导体（SOI）结构中的有源器件的主体去除过量载流子。 在一个实施例中，公开了一种制造集成电路的方法。 在一个步骤中，有源器件形成在绝缘体上半导体晶片的有源层中。 在另一步骤中，从设置在SOI晶片的背面的衬底层去除衬底材料。 在另一步骤中，从SOI晶片的背面去除绝缘体材料以形成挖掘的绝缘体区域。 在另一个步骤中，导电层沉积在挖掘的绝缘体区域上。 沉积导电层使其与挖掘的绝缘体区域的第一部分中的有源器件的主体物理接触。 导电层然后将本体连接到挖掘的绝缘体区域的第二分离部分中的触点。

公开(公告)号：US20110227637A1

公开(公告)日：2011-09-22

申请号：US13028144

申请日：2011-02-15

Applicant: Michael A. Stuber ,  Christopher N. Brindle ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George P. Imthurn ,  Mark L. Burgener ,  Alexander Dribinsky ,  Tae Youn Kim

Inventor： Michael A. Stuber ,  Christopher N. Brindle ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George P. Imthurn ,  Mark L. Burgener ,  Alexander Dribinsky ,  Tae Youn Kim

IPC: G05F1/10 ,  H01L29/772

CPC classification number: H01L29/78615 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78651 ,  H01L29/78654 ,  H01L29/78657 ,  H03K17/162

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

Abstract translation: 公开了一种用于使用累积电荷控制（ACC）技术来改善绝缘体上半导体（SOI）金属氧化物 - 硅场效应晶体管（MOSFET）器件的栅极氧化可靠性的方法和装置。 该方法和装置适于去除，减少或以其他方式控制SOI MOSFET中的累积电荷，从而产生FET性能特性的改进。 在一个实施例中，电路包括以累积电荷状态运行的MOSFET，以及用于控制可操作地耦合到SOI MOSFET的累积电荷的装置。 首先确定不受控制的累积电荷对SOI MOSFET的栅极氧化物的时间依赖介电击穿（TDDB）的影响。 第二次确定SOI MOSFET的栅极氧化物的受控累积电荷对TDDB的影响。 SOI MOSFET适于具有响应于第一和第二确定的选择的平均时间分辨率，并且使用用于可操作地耦合到SOI MOSFET的累积电荷控制的技术来操作电路。 在一个实施例中，累积的电荷控制技术包括使用可操作地耦合到SOI MOSFET体的累积电荷宿。

公开(公告)号：US07890891B2

公开(公告)日：2011-02-15

申请号：US11520912

申请日：2006-09-14

Applicant: Michael A. Stuber ,  Christopher N. Brindle ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George P. Imthurn ,  Robert B. Welstand ,  Mark L. Burgener ,  Alexander Dribinsky ,  Tae Youn Kim

Inventor： Michael A. Stuber ,  Christopher N. Brindle ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George P. Imthurn ,  Robert B. Welstand ,  Mark L. Burgener ,  Alexander Dribinsky ,  Tae Youn Kim

IPC: G06F17/50

CPC classification number: H01L29/78615 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78651 ,  H01L29/78654 ,  H01L29/78657 ,  H03K17/162

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

Abstract translation: 公开了一种用于使用累积电荷控制（ACC）技术来改善绝缘体上半导体（SOI）金属氧化物 - 硅场效应晶体管（MOSFET）器件的栅极氧化可靠性的方法和装置。 该方法和装置适于去除，减少或以其他方式控制SOI MOSFET中的累积电荷，从而产生FET性能特性的改进。 在一个实施例中，电路包括以累积电荷状态运行的MOSFET，以及用于控制可操作地耦合到SOI MOSFET的累积电荷的装置。 首先确定不受控制的累积电荷对SOI MOSFET的栅极氧化物的时间依赖介电击穿（TDDB）的影响。 第二次确定SOI MOSFET的栅极氧化物的受控累积电荷对TDDB的影响。 SOI MOSFET适于具有响应于第一和第二确定的选择的平均时间分辨率，并且使用用于可操作地耦合到SOI MOSFET的累积电荷控制的技术来操作电路。 在一个实施例中，累积的电荷控制技术包括使用可操作地耦合到SOI MOSFET体的累积电荷宿。

公开(公告)号：US09748272B2

公开(公告)日：2017-08-29

申请号：US13452836

申请日：2012-04-21

Applicant: Paul A. Nygaard ,  Stuart B. Molin ,  Michael A. Stuber

Inventor： Paul A. Nygaard ,  Stuart B. Molin ,  Michael A. Stuber

IPC: H01L29/20 ,  H01L21/20 ,  H01L23/36 ,  H01L33/12 ,  H01L27/12 ,  H01L21/78 ,  H01L21/84 ,  H01L23/367 ,  H01L29/786 ,  H01L21/762 ,  H01L23/00

CPC classification number: H01L27/1207 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/08225 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/29186 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/80006 ,  H01L2224/8022 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/83005 ,  H01L2224/8322 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92142 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/053 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2224/45099

Abstract: Embodiments of the present invention provide for the application of strain inducing layers to enhance the mobility of transistors formed on semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a strain inducing material is deposited on the excavated insulator region. The strain inducing material interacts with the pattern of excavated insulator such that a single layer provides both tensile and compressive stress to p-channel and n-channel transistors, respectively. In alternative embodiments, the entire substrate is removed before forming the strain inducing material.

公开(公告)号：US09029201B2

公开(公告)日：2015-05-12

申请号：US12836559

申请日：2010-07-14

Applicant: Paul A. Nygaard ,  Stuart B. Molin ,  Michael A. Stuber

Inventor： Paul A. Nygaard ,  Stuart B. Molin ,  Michael A. Stuber

IPC: H01L21/00 ,  H01L27/12 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/367 ,  H01L29/786 ,  H01L21/762 ,  H01L23/00

CPC classification number: H01L27/1207 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/08225 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/29186 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/80006 ,  H01L2224/8022 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/83005 ,  H01L2224/8322 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92142 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/053 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2224/45099

Abstract: Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.

Abstract translation: 本发明的实施例提供了绝缘体上半导体（SOI）结构的散热。 在一个实施例中，公开了一种用于制造集成电路的方法。 在第一步中，在SOI晶片的有源层中形成有源电路。 在第二步骤中，从设置在SOI晶片的背面的衬底层去除衬底材料。 在第三步骤中，从SOI晶片的背面去除绝缘体材料以形成挖掘的绝缘体区域。 在第四步骤中，散热层沉积在所述挖掘的绝缘体区域上。 散热层是导热和电绝缘的。

公开(公告)号：US08466036B2

公开(公告)日：2013-06-18

申请号：US13313231

申请日：2011-12-07

Applicant: Chris Brindle ,  Michael A. Stuber ,  Stuart B. Molin

Inventor： Chris Brindle ,  Michael A. Stuber ,  Stuart B. Molin

IPC: H01L21/30

CPC classification number: H01L29/1083 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2007 ,  H01L21/265 ,  H01L21/30 ,  H01L21/30604 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/528 ,  H01L24/09 ,  H01L24/83 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/08145 ,  H01L2224/27452 ,  H01L2224/27616 ,  H01L2224/80001 ,  H01L2224/838 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/00

Abstract: An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Abstract translation: 集成电路芯片形成有活性层和富集层。 有源层由有源器件层和金属互连层形成。 陷阱富层形成在有源层上方。 在一些实施例中，有源层包括在半导体晶片中，并且阱富层包含在处理晶片中。

公开(公告)号：US08232597B2

公开(公告)日：2012-07-31

申请号：US12836506

申请日：2010-07-14

Applicant: Michael A. Stuber ,  Stuart B. Molin ,  Paul A. Nygaard

Inventor： Michael A. Stuber ,  Stuart B. Molin ,  Paul A. Nygaard

IPC: H01L27/12

CPC classification number: H01L27/1207 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78606 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

Abstract: Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.

Abstract translation: 本发明的实施例提供从绝缘体上半导体（SOI）结构中的有源器件的主体去除过量载流子。 在一个实施例中，公开了一种制造集成电路的方法。 在一个步骤中，有源器件形成在绝缘体上半导体晶片的有源层中。 在另一步骤中，从设置在SOI晶片的背面的衬底层去除衬底材料。 在另一步骤中，从SOI晶片的背面去除绝缘体材料以形成挖掘的绝缘体区域。 在另一个步骤中，导电层沉积在挖掘的绝缘体区域上。 沉积导电层使其与挖掘的绝缘体区域的第一部分中的有源器件的主体物理接触。 导电层然后将本体连接到挖掘的绝缘体区域的第二分离部分中的触点。