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公开(公告)号：US06847369B2
公开(公告)日：2005-01-25
申请号：US10060915
申请日：2002-01-30
摘要： A data queue optimized for receiving loosely packed graphics data and suitable for use in a computer graphics system is described. The data queue operates on first-in-first-out principals, and has a variable width input and output. The variable width on the input side facilitates the reception and storage of loosely packed data. The variable width output allows for the single-cycle output of multi-word data. Packing of the data occurs on the write-side of the FIFO structure.
摘要翻译： 描述了优化用于接收松散封装的图形数据并适合于在计算机图形系统中使用的数据队列。 数据队列以先进先出原则进行操作，并具有可变宽度的输入和输出。 输入侧的可变宽度有助于松散打包数据的接收和存储。 可变宽度输出允许多字数据的单周期输出。 数据的包装发生在FIFO结构的写入端。
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公开(公告)号：US07027064B2
公开(公告)日：2006-04-11
申请号：US10086174
申请日：2002-02-28
CPC分类号： G09G5/39 , G06F12/0804 , G06F12/0897 , G06F12/126 , G06F2212/455 , G06T1/60 , G09G2360/121
摘要： An external cache management unit for use with 3D-RAM and suitable for use in a computer graphics system is described. The unit maintains and tracks the status of level one cache memory in the 3D-RAM. The unit identifies dirty blocks of cache memory and prioritizes block cleansing based on a least used algorithm. Periodic block cleansing during empty memory cycles is provided for, and may also be prompted on demand.
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3.发明授权Multi-texturing by walking an appropriately-sized supertile over a primitive 有权通过在原始图像上行走适当尺寸的超重物进行多纹理化公开(公告)号：US07023444B2
公开(公告)日：2006-04-04
申请号：US10393528
申请日：2003-03-20
申请人： Brian D. Emberling , Michael G. Lavelle , Assana M. Fard , Nandini Ramani , David C. Kehlet , Michael A. Wasserman , Ewa M. Kubalska , Mark E Pascual
发明人： Brian D. Emberling , Michael G. Lavelle , Assana M. Fard , Nandini Ramani , David C. Kehlet , Michael A. Wasserman , Ewa M. Kubalska , Mark E Pascual
IPC分类号： G06T11/40
CPC分类号： G06T15/04
摘要： A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.
摘要翻译： 渲染单元定位一个supertile，以便它与一个原语相交。 渲染单元重复地移动超重物料箱，在所述重复步行的每次迭代中将一层纹理施加到上层的仓上。 渲染单元在将当前纹理层应用于上层的每个候选块之后前进到下一个纹理层。 每个纹理层应用于存储区的结果可以存储在纹理累积缓冲器中。 supertile的大小对应于纹理累积缓冲区的大小。 将最后一层纹理应用于上层的仓后，超级可以提前到一个新的位置。 渲染单元用优先级遍历原始图像，使得由supertile访问的区域的联合覆盖原始图像。
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公开(公告)号：US5579473A
公开(公告)日：1996-11-26
申请号：US276814
申请日：1994-07-18
IPC分类号： G06F12/00 , C04B28/08 , G06F12/08 , G06T11/00 , G09G5/00 , G09G5/39 , G09G5/393 , G09G5/397 , G09G5/399 , G06F15/00
CPC分类号： G09G5/393 , G06F12/0897 , G09G5/39 , G09G2360/121 , G09G2360/123
摘要： A frame buffer memory device controller that schedules and dispatches operations to frame buffer memory devices is disclosed. The frame buffer memory device controller schedules and dispatches cache control operations to reduce timing overheads caused by cache prefetch operations, and operations to write back dirty cache lines and clear cache lines in the frame buffer memory devices. The frame buffer memory device controller also schedules and dispatches control operations to reduce timing overheads caused by video refresh operations from the frame buffer memory devices video output ports.
摘要翻译： 公开了一种对帧缓冲存储器件进行调度和调度操作的帧缓冲存储器件控制器。 帧缓冲存储器设备控制器调度和调度高速缓存控制操作以减少由高速缓存预取操作引起的定时开销，以及写入脏高速缓存行并清除帧缓冲存储器设备中的高速缓存行的操作。 帧缓冲存储器件控制器还调度和调度控制操作以减少由帧缓冲存储器件视频输出端口的视频刷新操作引起的定时开销。
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5.发明授权公开(公告)号：US06859209B2
公开(公告)日：2005-02-22
申请号：US09861468
申请日：2001-05-18
申请人： Michael G. Lavelle , Brian D. Emberling , Ranjit S. Oberoi , Deron D. Johnson , Ewa M. Kubalska
发明人： Michael G. Lavelle , Brian D. Emberling , Ranjit S. Oberoi , Deron D. Johnson , Ewa M. Kubalska
CPC分类号： G09G5/363 , G06T11/40 , G06T15/005
摘要： A graphics system applies multiple layers of texture information to triangles. The graphics system includes a hardware accelerator, a frame buffer and a video output processor. The hardware accelerator receives vertices of a triangle, identifies fragments of a sampling space which intersect the triangle, and applies the multiple layers of texture to the intersecting fragments. The multiple layers of textures may be stored in a texture memory external to the hardware accelerator. The hardware accelerator switches to a next texture layer after applying the textures of a current layer to all the fragments of the triangle. The hardware accelerator includes (or couples to) a texture accumulation buffer which stores color values associated with the triangle fragments between the application of successive texture layers. The frame buffer stores the samples and pixels generated from the samples by filtration. The video output processor transforms the pixels into a video signal.
摘要翻译： 图形系统将多层纹理信息应用于三角形。 图形系统包括硬件加速器，帧缓冲器和视频输出处理器。 硬件加速器接收三角形的顶点，识别与三角形相交的采样空间的片段，并将多层纹理应用于相交片段。 多层纹理可以存储在硬件加速器外部的纹理存储器中。 硬件加速器在将当前层的纹理应用于三角形的所有片段之后切换到下一个纹理层。 硬件加速器包括（或耦合到）纹理累积缓冲器，其存储与连续纹理层的应用之间的三角形片段相关联的颜色值。 帧缓冲器通过过滤存储从样本产生的样本和像素。 视频输出处理器将像素转换为视频信号。
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6.发明授权Rasterization using two-dimensional tiles and alternating bins for improved rendering utilization 有权使用二维瓦片和交替箱体进行光栅化，以提高渲染利用率公开(公告)号：US06803916B2
公开(公告)日：2004-10-12
申请号：US09861475
申请日：2001-05-18
申请人： Nandini Ramani , David C. Kehlet , Ewa M. Kubalska , Michael G. Lavelle , Michael A. Wasserman , Kevin Tang , Yan Yan Tang
发明人： Nandini Ramani , David C. Kehlet , Ewa M. Kubalska , Michael G. Lavelle , Michael A. Wasserman , Kevin Tang , Yan Yan Tang
IPC分类号： G06T120
摘要： A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the system's rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.
摘要翻译： 公开了一种用于光栅化和渲染图形数据的系统和方法。 顶点可以被分组以形成诸如三角形的图元，其使用样本仓的二维阵列进行光栅化。 可以根据诸如存储体分配的不同标准从箱中选择单个样本，以提高系统的渲染管线的利用率。 由于阵列可以具有比渲染流水线中的评估单元数更多的存储单元，所以来自存储区的样本可以被存储到FIFO存储器中以允许去除无效或空的样本（被渲染的原始图像之外的样本）。 然后可以对样本进行滤波以形成可显示以在显示装置上形成图像的像素。
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公开(公告)号：US06778179B2
公开(公告)日：2004-08-17
申请号：US09970113
申请日：2001-10-03
IPC分类号： G09G536
CPC分类号： G06F12/0897 , G06T1/60 , G06T15/005 , G09G5/363 , G09G5/39 , G09G2360/121 , G09G2360/122 , Y02D10/13
摘要： An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.
摘要翻译： 描述了一种用于3D-RAM帧缓冲器并适用于计算机图形系统的外部高速缓存管理单元。 该单元可以通过根据存储在脏标签位阵列中的状态信息执行部分块回写来减少3D-RAM内的功耗。 在空的存储器循环期间提供了周期性的一级缓存块清理。
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公开(公告)号：US06833834B2
公开(公告)日：2004-12-21
申请号：US10021096
申请日：2001-12-12
IPC分类号： G06F1300
CPC分类号： G09G3/006 , G06F3/1431 , G09G5/001 , G09G5/18 , G09G5/363 , G09G5/395 , G09G2360/123
摘要： A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.
摘要翻译： 图形系统包括帧缓冲器，写地址生成器和像素缓冲器。 从帧缓冲器接收到的像素突发可能不是显示顺序。 在一个实施例中，写地址生成器计算从帧缓冲器输出的像素突发中的每个像素的写入地址。 写入地址对应于每个相应像素的突发内的相对显示顺序。 突发中的每个像素被存储到像素缓冲器中的其写入地址。 这样，突发中的像素以像素缓冲器内的显示顺序存储。
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公开(公告)号：US06720969B2
公开(公告)日：2004-04-13
申请号：US09861172
申请日：2001-05-18
IPC分类号： G09G536
CPC分类号： G06F12/0897 , G06T1/60 , G06T15/005 , G09G5/363 , G09G5/39 , G09G2360/121 , G09G2360/122 , Y02D10/13
摘要： An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.
摘要翻译： 描述了一种用于3D-RAM帧缓冲器并适用于计算机图形系统的外部高速缓存管理单元。 该单元可以通过根据存储在脏标签位阵列中的状态信息执行部分块回写来减少3D-RAM内的功耗。 在空的存储器循环期间提供了周期性的一级缓存块清理。
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公开(公告)号：US06661423B2
公开(公告)日：2003-12-09
申请号：US09861184
申请日：2001-05-18
IPC分类号： G06F1206
CPC分类号： G06T1/60
摘要： A memory array management unit suitable for use in a computer graphics system is described. The unit is especially designed to facilitate the storage of tiles of graphics data. Alignment detection between the tiles and memory block boundaries is provided for, with misalignments resulting in the automatic decimation to produce sub-tiles and generation of multiple memory write sequences.
摘要翻译： 描述适用于计算机图形系统的存储器阵列管理单元。 该单元特别设计用于方便存储图形数据的瓦片。 提供了瓦片和存储器块边界之间的对准检测，其中未对准导致自动抽取以产生子图块并生成多个存储器写入序列。
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