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    Forming facet-less epitaxy with self-aligned isolation
    1.
    发明授权
    Forming facet-less epitaxy with self-aligned isolation 有权
    用自对准隔离形成无面外延

    公开(公告)号：US08969163B2

    公开(公告)日：2015-03-03

    申请号：US13556406

    申请日：2012-07-24

    申请人： Michael V. Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    发明人： Michael V. Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/70

    CPC分类号： H01L21/76232 ,  H01L29/66628 ,  H01L29/66636

    摘要： A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between a first and a second one of the plurality of gates, whereby the first and second gates are adjacent. A second raised epitaxial layer may be deposited on another recessed region of the continuous active layer between the second and a third one of the plurality of gates, whereby the second and third gates are adjacent. Using a cut mask, a trench structure is etched into the second gate structure and a region underneath the second gate in the continuous active layer. The trench is filled with isolation material for electrically isolating the first and second raised epitaxial layers.

    摘要翻译： 形成半导体结构的方法可以包括在衬底的区域中制备连续有源层，并在连续有源层上形成多个相邻栅极。 第一凸起的外延层可以沉积在多个栅极中的第一和第二栅极之间的连续有源层的凹陷区域上，由此第一和第二栅极相邻。 第二凸起的外延层可以沉积在多个栅极中的第二和第三栅极之间的连续有源层的另一个凹陷区域上，由此第二和第三栅极相邻。 使用切割掩模，沟槽结构被蚀刻到第二栅极结构中以及连续有源层中的第二栅极下方的区域。 沟槽填充有用于电隔离第一和第二凸起外延层的隔离材料。

    FORMING FACET-LESS EPITAXY WITH SELF-ALIGNED ISOLATION
    2.
    发明申请
    FORMING FACET-LESS EPITAXY WITH SELF-ALIGNED ISOLATION 有权
    具有自对准隔离的成形面较小的外观

    公开(公告)号：US20140027820A1

    公开(公告)日：2014-01-30

    申请号：US13556406

    申请日：2012-07-24

    申请人： Michael V. Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    发明人： Michael V. Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L21/76232 ,  H01L29/66628 ,  H01L29/66636

    摘要： A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between a first and a second one of the plurality of gates, whereby the first and second gates are adjacent. A second raised epitaxial layer may be deposited on another recessed region of the continuous active layer between the second and a third one of the plurality of gates, whereby the second and third gates are adjacent. Using a cut mask, a trench structure is etched into the second gate structure and a region underneath the second gate in the continuous active layer. The trench is filled with isolation material for electrically isolating the first and second raised epitaxial layers.

    摘要翻译： 形成半导体结构的方法可以包括在衬底的区域中制备连续有源层，并在连续有源层上形成多个相邻栅极。 第一凸起的外延层可以沉积在多个栅极中的第一和第二栅极之间的连续有源层的凹陷区域上，由此第一和第二栅极相邻。 第二凸起的外延层可以沉积在多个栅极中的第二和第三栅极之间的连续有源层的另一个凹陷区域上，由此第二和第三栅极相邻。 使用切割掩模，沟槽结构被蚀刻到第二栅极结构中以及连续有源层中的第二栅极下方的区域。 沟槽填充有用于电隔离第一和第二凸起外延层的隔离材料。

    FORMING FACET-LESS EPITAXY WITH A CUT MASK
    3.
    发明申请
    FORMING FACET-LESS EPITAXY WITH A CUT MASK 有权
    用切割面膜形成面积小的外观

    公开(公告)号：US20130313647A1

    公开(公告)日：2013-11-28

    申请号：US13478411

    申请日：2012-05-23

    申请人： Michael Vincent Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    发明人： Michael Vincent Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    IPC分类号： H01L21/8234 ,  H01L27/088

    CPC分类号： H01L21/823807 ,  H01L21/76897 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/78

    摘要： A method of forming a semiconductor structure on a substrate is provided. The method may include preparing a continuous active layer on a region of the substrate and depositing a first raised epitaxial layer on a first region of the continuous active layer. A second raised epitaxial layer is also deposited on a second region of the continuous active layer such that the first raised epitaxial layer is in close proximity to the second raised epitaxial layer. A mask may be used to etch a trench structure into the continuous active layer at both the first and the second raised epitaxial layer, whereby the etched trench structure is filled with isolation material for electrically isolating the first raised epitaxial layer from the second raised epitaxial layer.

    摘要翻译： 提供了在基板上形成半导体结构的方法。 该方法可以包括在衬底的区域上制备连续的有源层并且在连续有源层的第一区域上沉积第一凸起的外延层。 第二凸起外延层也沉积在连续有源层的第二区上，使得第一凸起外延层紧邻第二凸起外延层。 可以使用掩模将沟槽结构蚀刻到第一和第二凸起外延层两端的连续有源层，由此蚀刻沟槽结构填充有用于将第一凸起外延层与第二凸起外延层电隔离的隔离材料 。

    Forming facet-less epitaxy with a cut mask
    4.
    发明授权
    Forming facet-less epitaxy with a cut mask 有权
    用切割面罩形成小面外延

    公开(公告)号：US08658486B2

    公开(公告)日：2014-02-25

    申请号：US13478411

    申请日：2012-05-23

    申请人： Michael Vincent Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    发明人： Michael Vincent Aquilino ,  Byeong Yeol Kim ,  Ying Li ,  Carl John Radens

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/76897 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/78

    摘要： A method of forming a semiconductor structure on a substrate is provided. The method may include preparing a continuous active layer on a region of the substrate and depositing a first raised epitaxial layer on a first region of the continuous active layer. A second raised epitaxial layer is also deposited on a second region of the continuous active layer such that the first raised epitaxial layer is in close proximity to the second raised epitaxial layer. A mask may be used to etch a trench structure into the continuous active layer at both the first and the second raised epitaxial layer, whereby the etched trench structure is filled with isolation material for electrically isolating the first raised epitaxial layer from the second raised epitaxial layer.

    摘要翻译： 提供了在基板上形成半导体结构的方法。 该方法可以包括在衬底的区域上制备连续的有源层并且在连续有源层的第一区域上沉积第一凸起的外延层。 第二凸起外延层也沉积在连续有源层的第二区上，使得第一凸起外延层紧邻第二凸起外延层。 可以使用掩模将沟槽结构蚀刻到第一和第二凸起外延层两端的连续有源层，由此蚀刻沟槽结构填充有用于将第一凸起外延层与第二凸起外延层电隔离的隔离材料 。

    SEMICONDUCTOR CAPACITORS IN HOT (HYBRID ORIENTATION TECHNOLOGY) SUBSTRATES
    6.
    发明申请
    SEMICONDUCTOR CAPACITORS IN HOT (HYBRID ORIENTATION TECHNOLOGY) SUBSTRATES 失效
    半导体电容器（混合方向技术）衬底

    公开(公告)号：US20070284640A1

    公开(公告)日：2007-12-13

    申请号：US11423284

    申请日：2006-06-09

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl John Radens

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl John Radens

    IPC分类号： H01L29/94

    CPC分类号： H01L29/945 ,  H01L29/66931

    摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region.

    摘要翻译： 半导体结构及其形成方法。 半导体结构包括半导体衬底。 半导体结构还包括在半导体衬底的顶部上的电绝缘区域。 半导体结构还包括在半导体衬底之上并与之直接物理接触的第一半导体区域。 半导体结构还包括在绝缘区域的顶部上的第二半导体区域。 半导体结构还包括在第一半导体区域和半导体衬底中的电容器。 半导体结构还包括在第二半导体区域和电绝缘区域中的电容器电极接触。

    Structure and method of fabricating embedded DRAM having a vertical device array and a bordered bitline contact
    8.
    发明授权
    Structure and method of fabricating embedded DRAM having a vertical device array and a bordered bitline contact 有权
    制造具有垂直器件阵列和边界位线接触的嵌入式DRAM的结构和方法

    公开(公告)号：US06727540B2

    公开(公告)日：2004-04-27

    申请号：US10227404

    申请日：2002-08-23

    申请人： Ramachandra Divakaruni ,  Babar Ali Khan ,  Carl John Radens

    发明人： Ramachandra Divakaruni ,  Babar Ali Khan ,  Carl John Radens

    IPC分类号： H01L27108

    CPC分类号： H01L27/10891 ,  H01L27/0207 ,  H01L27/10864

    摘要： An integrated circuit including a dynamic random access memory (DRAM) array is disclosed herein in which a DRAM cell includes a storage capacitor within a deep trench, a transistor having a channel extending along a sidewall of the deep trench and a gate conductor within the deep trench, and a wordline contacting the gate conductor from above, wherein the wordline has a centerline which is offset from the centerline of the gate conductor. The DRAM cell further includes active area extending from the transistor channel, and a bitline contact to the active area which is bordered by an insulating spacer of the sidewall of the wordline.

    摘要翻译： 本文公开了一种包括动态随机存取存储器（DRAM）阵列的集成电路，其中DRAM单元在深沟槽内包括存储电容器，具有沿着深沟槽的侧壁延伸的沟道的晶体管和深沟槽内的栅极导体 沟槽和从上方接触栅极导体的字线，其中字线具有偏离栅极导体的中心线的中心线。 DRAM单元进一步包括从晶体管沟道延伸的有源区和与由字线的侧壁的绝缘间隔物界定的有源区的位线接触。

    Method of simultaneously forming a line interconnect and a borderless contact to diffusion
    9.
    发明授权
    Method of simultaneously forming a line interconnect and a borderless contact to diffusion 失效
    同时形成线路互连和无边界接触到扩散的方法

    公开(公告)号：US06245651B1

    公开(公告)日：2001-06-12

    申请号：US09481916

    申请日：2000-01-12

    申请人： Rama Divakaruni ,  Larry Alan Nesbit ,  Carl John Radens

    发明人： Rama Divakaruni ,  Larry Alan Nesbit ,  Carl John Radens

    IPC分类号： H01L213205

    CPC分类号： H01L27/10894 ,  H01L21/76802 ,  H01L27/10888

    摘要： A method for simultaneously forming a line interconnect such as a bitline and a borderless contact to diffusion, e.g. bitline contact, is described. A semiconductor substrate having prepatterned gate stacks thereon is covered with a first dielectric to form a first level and then a second dielectric is deposited which forms a second level. Line interconnect openings are defined in the second level by lithography and etching. Etching is continued down to monocrystalline regions in an array region of the substrate to form borderless contact openings coincident to the line interconnects between the gate stacks. The openings are filled with one or more conductors to form contacts to diffusion, e.g. bitline contacts, which are coincident to the line interconnects, e.g. bitlines.

    摘要翻译： 用于同时形成诸如位线和无边界接触之类的线互连的扩散的方法，例如。 描述了位线接触。 其上具有形成图案化栅极堆叠的半导体衬底被第一电介质覆盖以形成第一电平，然后沉积形成第二电平的第二电介质。 线路互连开口通过光刻和蚀刻在第二层限定。 在衬底的阵列区域中继续蚀刻到单晶区域以形成与栅叠层之间的线互连一致的无边界接触开口。 开口填充有一个或多个导体以形成扩散接触，例如。 位线接触，其与线互连一致，例如。 位线