公开(公告)号：US20050017746A1

公开(公告)日：2005-01-27

申请号：US10895833

申请日：2004-07-22

申请人： Michikazu Matsumoto ,  Yasutoshi Okuno ,  Katsuyoshi Joukyu ,  Tetsuya Matsutani

发明人： Michikazu Matsumoto ,  Yasutoshi Okuno ,  Katsuyoshi Joukyu ,  Tetsuya Matsutani

IPC分类号： G01R31/08 ,  G01R31/28

CPC分类号： G01R31/2884 ,  G01R31/2853

摘要： A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device including test patterns capable of measuring a resistance variation component to be the resistance variation defect in each chip area or each shot area of the wafer, wherein the number of test patterns included in one chip area or one shot area is set so that it is possible to estimate the yield of the integrated circuit device.

摘要翻译： 一种电阻缺陷评估装置，设置在用于评估集成电路器件的部件中的电阻变化缺陷的晶片上，所述电阻缺陷评估装置包括能够测量每个芯片区域中的电阻变化分量的电阻变化分量作为电阻变化缺陷的测试图案， 晶片的每个照射区域，其中设置包括在一个芯片区域或一个照射区域中的测试图案的数量，使得可以估计集成电路器件的产量。

公开(公告)号：US07253436B2

公开(公告)日：2007-08-07

申请号：US10895833

申请日：2004-07-22

申请人： Michikazu Matsumoto ,  Yasutoshi Okuno ,  Katsuyoshi Joukyu ,  Tetsuya Matsutani

发明人： Michikazu Matsumoto ,  Yasutoshi Okuno ,  Katsuyoshi Joukyu ,  Tetsuya Matsutani

IPC分类号： H01L23/58

CPC分类号： G01R31/2884 ,  G01R31/2853

摘要： A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device including test patterns capable of measuring a resistance variation component to be the resistance variation defect in each chip area or each shot area of the wafer, wherein the number of test patterns included in one chip area or one shot area is set so that it is possible to estimate the yield of the integrated circuit device.

摘要翻译： 一种电阻缺陷评估装置，设置在用于评估集成电路器件的部件中的电阻变化缺陷的晶片上，所述电阻缺陷评估装置包括能够测量每个芯片区域中的电阻变化分量的电阻变化分量作为电阻变化缺陷的测试图案， 晶片的每个照射区域，其中设置包括在一个芯片区域或一个照射区域中的测试图案的数量，使得可以估计集成电路器件的产量。

公开(公告)号：US20070093047A1

公开(公告)日：2007-04-26

申请号：US11582556

申请日：2006-10-18

申请人： Yasutoshi Okuno ,  Michikazu Matsumoto ,  Masafumi Kubota ,  Seiji Ueda ,  Hiroshi Iwai ,  Kazuo Tsutsui ,  Kuniyuki Kakushima

发明人： Yasutoshi Okuno ,  Michikazu Matsumoto ,  Masafumi Kubota ,  Seiji Ueda ,  Hiroshi Iwai ,  Kazuo Tsutsui ,  Kuniyuki Kakushima

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions. In the step of forming the nickel alloy silicide layer, a nickel alloy film and a nickel film are sequentially deposited on the semiconductor substrate and thereafter subjected to heat treatment.

摘要翻译： 在包含硅的半导体衬底上形成栅电极，然后在位于栅电极两侧的半导体衬底的区域中形成源极/漏极区，然后在栅极上至少形成一个镍合金硅化物层 或源极/漏极区域。 在形成镍合金硅化物层的步骤中，在半导体衬底上依次沉积镍合金膜和镍膜，然后进行热处理。

公开(公告)号：US07800181B2

公开(公告)日：2010-09-21

申请号：US11582556

申请日：2006-10-18

申请人： Yasutoshi Okuno ,  Michikazu Matsumoto ,  Masafumi Kubota ,  Seiji Ueda ,  Hiroshi Iwai ,  Kazuo Tsutsui ,  Kuniyuki Kakushima

发明人： Yasutoshi Okuno ,  Michikazu Matsumoto ,  Masafumi Kubota ,  Seiji Ueda ,  Hiroshi Iwai ,  Kazuo Tsutsui ,  Kuniyuki Kakushima

IPC分类号： H01L29/78

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions. In the step of forming the nickel alloy silicide layer, a nickel alloy film and a nickel film are sequentially deposited on the semiconductor substrate and thereafter subjected to heat treatment.

摘要翻译： 在包含硅的半导体衬底上形成栅电极，然后在位于栅电极两侧的半导体衬底的区域中形成源极/漏极区，然后在栅极上至少形成一个镍合金硅化物层 或源极/漏极区域。 在形成镍合金硅化物层的步骤中，在半导体衬底上依次沉积镍合金膜和镍膜，然后进行热处理。

公开(公告)号：US07202147B2

公开(公告)日：2007-04-10

申请号：US11288093

申请日：2005-11-29

申请人： Yasutoshi Okuno ,  Michikazu Matsumoto

发明人： Yasutoshi Okuno ,  Michikazu Matsumoto

IPC分类号： H01L29/06 ,  H01L21/336

CPC分类号： H01L21/823443 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide.

公开(公告)号：US20060138562A1

公开(公告)日：2006-06-29

申请号：US11288093

申请日：2005-11-29

申请人： Yasutoshi Okuno ,  Michikazu Matsumoto

发明人： Yasutoshi Okuno ,  Michikazu Matsumoto

IPC分类号： H01L29/76 ,  H01L21/3205

CPC分类号： H01L21/823443 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide.

摘要翻译： 半导体器件包括：形成在硅衬底上的栅电极; 形成在硅衬底中的栅电极的两侧的源/漏区; 以及形成在源极/漏极区上的硅化物层。 硅化物层包括主要由金属硅化物形成的第一硅化物层，其形成焓低于NiSi的形成焓，以及在第一硅化物上形成并由Ni硅化物制成的第二硅化物层。

公开(公告)号：US20060189087A1

公开(公告)日：2006-08-24

申请号：US11356959

申请日：2006-02-21

申请人： Yasutoshi Okuno ,  Michikazu Matsumoto

发明人： Yasutoshi Okuno ,  Michikazu Matsumoto

IPC分类号： H01L21/336

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： A gate electrode is formed on a silicon substrate, and then source/drain regions are formed at both sides of the gate electrode in the silicon substrate. Thereafter, an alloyed silicide layer is formed on the source/drain regions. The step of forming the alloyed silicide layer includes the step of depositing a first metal film, a nickel film and a second metal film in this order to form a multilayer metal film and the step of performing heat treatment after the formation of the multilayer metal film.

公开(公告)号：US07585767B2

公开(公告)日：2009-09-08

申请号：US11356959

申请日：2006-02-21

申请人： Yasutoshi Okuno ,  Michikazu Matsumoto

发明人： Yasutoshi Okuno ,  Michikazu Matsumoto

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： A gate electrode is formed on a silicon substrate, and then source/drain regions are formed at both sides of the gate electrode in the silicon substrate. Thereafter, an alloyed silicide layer is formed on the source/drain regions. The step of forming the alloyed silicide layer includes the step of depositing a first metal film, a nickel film and a second metal film in this order to form a multilayer metal film and the step of performing heat treatment after the formation of the multilayer metal film.

摘要翻译： 在硅衬底上形成栅电极，然后在硅衬底中的栅电极的两侧形成源/漏区。 此后，在源极/漏极区域上形成合金化的硅化物层。 形成合金化硅化物层的步骤包括依次沉积第一金属膜，镍膜和第二金属膜以形成多层金属膜的步骤，以及在形成多层金属膜之后进行热处理的步骤 。

公开(公告)号：US20070158760A1

公开(公告)日：2007-07-12

申请号：US11723061

申请日：2007-03-16

申请人： Yasutoshi Okuno ,  Michikazu Matsumoto

发明人： Yasutoshi Okuno ,  Michikazu Matsumoto

IPC分类号： H01L29/76 ,  H01L21/4763

CPC分类号： H01L21/26506 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide.

摘要翻译： 半导体器件包括：形成在硅衬底上的栅电极; 形成在硅衬底中的栅电极的两侧的源/漏区; 以及形成在源极/漏极区上的硅化物层。 硅化物层包括主要由金属硅化物形成的第一硅化物层，其形成焓低于NiSi的形成焓，以及在第一硅化物上形成并由Ni硅化物制成的第二硅化物层。

公开(公告)号：US20060187719A1

公开(公告)日：2006-08-24

申请号：US11240553

申请日：2005-10-03

申请人： Michikazu Matsumoto ,  Yasutoshi Okuno ,  Kazuyoshi Tsukamoto ,  Toshiki Yabu

发明人： Michikazu Matsumoto ,  Yasutoshi Okuno ,  Kazuyoshi Tsukamoto ,  Toshiki Yabu

IPC分类号： G11C7/10

CPC分类号： H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/29139 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0401

摘要： In ID generation for a semiconductor package or a semiconductor integrated circuit chip, a topographic characteristic to be utilized as specific information is selected from at least one topographic characteristic that the semiconductor package or the semiconductor integrated circuit has. Then, the selected topographic characteristic is measured as the specific information and an ID for identification is generated for the semiconductor package or the semiconductor integrated circuit chip based on the measured specific information.

摘要翻译： 在半导体封装或半导体集成电路芯片的ID生成中，从半导体封装或半导体集成电路具有的至少一个地形特征中选择要用作特定信息的地形特征。 然后，测量所选择的地形特征作为特定信息，并且基于所测量的特定信息为半导体封装或半导体集成电路芯片生成用于识别的ID。