公开(公告)号：US20060187719A1

公开(公告)日：2006-08-24

申请号：US11240553

申请日：2005-10-03

申请人： Michikazu Matsumoto ,  Yasutoshi Okuno ,  Kazuyoshi Tsukamoto ,  Toshiki Yabu

发明人： Michikazu Matsumoto ,  Yasutoshi Okuno ,  Kazuyoshi Tsukamoto ,  Toshiki Yabu

IPC分类号： G11C7/10

CPC分类号： H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/29139 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0401

摘要： In ID generation for a semiconductor package or a semiconductor integrated circuit chip, a topographic characteristic to be utilized as specific information is selected from at least one topographic characteristic that the semiconductor package or the semiconductor integrated circuit has. Then, the selected topographic characteristic is measured as the specific information and an ID for identification is generated for the semiconductor package or the semiconductor integrated circuit chip based on the measured specific information.

摘要翻译： 在半导体封装或半导体集成电路芯片的ID生成中，从半导体封装或半导体集成电路具有的至少一个地形特征中选择要用作特定信息的地形特征。 然后，测量所选择的地形特征作为特定信息，并且基于所测量的特定信息为半导体封装或半导体集成电路芯片生成用于识别的ID。

公开(公告)号：US07126174B2

公开(公告)日：2006-10-24

申请号：US10995283

申请日：2004-11-24

申请人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

发明人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

IPC分类号： H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/76224 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

摘要翻译： 形成了比硅衬底的有源区域更高级的隔离。 在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。 绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。 不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。 由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中杂质浓度低的部分接触。 以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。

公开(公告)号：US5726479A

公开(公告)日：1998-03-10

申请号：US584123

申请日：1996-01-11

申请人： Michikazu Matsumoto ,  Minoru Fujii ,  Toshiki Yabu

发明人： Michikazu Matsumoto ,  Minoru Fujii ,  Toshiki Yabu

IPC分类号： H01L23/532 ,  H01L29/49 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/4933 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/903

摘要： A polysilicon electrode is formed in an active area surrounded by an isolation on a silicon substrate with a gate oxide film sandwiched therebetween, a polysilicon wire is formed on the isolation, and a source/drain region is formed on both sides of the polysilicon electrode. On the both sides of a polysilicon film constituting the electrode and the wire are formed side walls having a height that is 4/5 or less of the height of the polysilicon film. Furthermore, the polysilicon film is provided with a silicide layer in contact with the top surface and portions of the side surfaces of the polysilicon film projecting from the side walls, and another silicide layer is formed in contact with the source/drain region. Since the sectional area of the silicide layer is increased, the resistance value can be suppressed even when the dimension of the polysilicon film is minimized. Thus, the invention provides a semiconductor device including an FET having a low resistance value applicable to a refined pattern.

摘要翻译： 在由硅衬底上的隔离包围的有源区域中形成多晶硅电极，其间夹有栅极氧化膜，在隔离层上形成多晶硅导线，并在多晶硅电极的两侧形成源极/漏极区域。 在构成电极和导线的多晶硅膜的两侧形成高度为多晶硅膜的高度为+ E，fra 4/5 + EE以下的侧壁。 此外，多晶硅膜设置有与侧壁突出的顶表面和多晶硅膜的侧表面的部分接触的硅化物层，并且另外的硅化物层形成为与源极/漏极区域接触。 由于硅化物层的截面积增加，所以即使当多晶硅膜的尺寸最小化时也可以抑制电阻值。 因此，本发明提供一种包括具有适用于精细图案的低电阻值的FET的半导体器件。

公开(公告)号：US20070093047A1

公开(公告)日：2007-04-26

申请号：US11582556

申请日：2006-10-18

申请人： Yasutoshi Okuno ,  Michikazu Matsumoto ,  Masafumi Kubota ,  Seiji Ueda ,  Hiroshi Iwai ,  Kazuo Tsutsui ,  Kuniyuki Kakushima

发明人： Yasutoshi Okuno ,  Michikazu Matsumoto ,  Masafumi Kubota ,  Seiji Ueda ,  Hiroshi Iwai ,  Kazuo Tsutsui ,  Kuniyuki Kakushima

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions. In the step of forming the nickel alloy silicide layer, a nickel alloy film and a nickel film are sequentially deposited on the semiconductor substrate and thereafter subjected to heat treatment.

摘要翻译： 在包含硅的半导体衬底上形成栅电极，然后在位于栅电极两侧的半导体衬底的区域中形成源极/漏极区，然后在栅极上至少形成一个镍合金硅化物层 或源极/漏极区域。 在形成镍合金硅化物层的步骤中，在半导体衬底上依次沉积镍合金膜和镍膜，然后进行热处理。

公开(公告)号：US20050093089A1

公开(公告)日：2005-05-05

申请号：US10995283

申请日：2004-11-24

申请人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

发明人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L29/00

CPC分类号： H01L29/6659 ,  H01L21/76224 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

摘要翻译： 形成了比硅衬底的有源区域更高级的隔离。 在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。 绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。 不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。 由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中杂质浓度低的部分接触。 以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。

公开(公告)号：US06967409B2

公开(公告)日：2005-11-22

申请号：US10454682

申请日：2003-06-05

申请人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

发明人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L29/40

CPC分类号： H01L29/6659 ,  H01L21/76224 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

公开(公告)号：US07800181B2

公开(公告)日：2010-09-21

申请号：US11582556

申请日：2006-10-18

申请人： Yasutoshi Okuno ,  Michikazu Matsumoto ,  Masafumi Kubota ,  Seiji Ueda ,  Hiroshi Iwai ,  Kazuo Tsutsui ,  Kuniyuki Kakushima

发明人： Yasutoshi Okuno ,  Michikazu Matsumoto ,  Masafumi Kubota ,  Seiji Ueda ,  Hiroshi Iwai ,  Kazuo Tsutsui ,  Kuniyuki Kakushima

IPC分类号： H01L29/78

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions. In the step of forming the nickel alloy silicide layer, a nickel alloy film and a nickel film are sequentially deposited on the semiconductor substrate and thereafter subjected to heat treatment.

摘要翻译： 在包含硅的半导体衬底上形成栅电极，然后在位于栅电极两侧的半导体衬底的区域中形成源极/漏极区，然后在栅极上至少形成一个镍合金硅化物层 或源极/漏极区域。 在形成镍合金硅化物层的步骤中，在半导体衬底上依次沉积镍合金膜和镍膜，然后进行热处理。

公开(公告)号：US07202147B2

公开(公告)日：2007-04-10

申请号：US11288093

申请日：2005-11-29

申请人： Yasutoshi Okuno ,  Michikazu Matsumoto

发明人： Yasutoshi Okuno ,  Michikazu Matsumoto

IPC分类号： H01L29/06 ,  H01L21/336

CPC分类号： H01L21/823443 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide.

公开(公告)号：US20060138562A1

公开(公告)日：2006-06-29

申请号：US11288093

申请日：2005-11-29

申请人： Yasutoshi Okuno ,  Michikazu Matsumoto

发明人： Yasutoshi Okuno ,  Michikazu Matsumoto

IPC分类号： H01L29/76 ,  H01L21/3205

CPC分类号： H01L21/823443 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide.

摘要翻译： 半导体器件包括：形成在硅衬底上的栅电极; 形成在硅衬底中的栅电极的两侧的源/漏区; 以及形成在源极/漏极区上的硅化物层。 硅化物层包括主要由金属硅化物形成的第一硅化物层，其形成焓低于NiSi的形成焓，以及在第一硅化物上形成并由Ni硅化物制成的第二硅化物层。

公开(公告)号：US20050017746A1

公开(公告)日：2005-01-27

申请号：US10895833

申请日：2004-07-22

申请人： Michikazu Matsumoto ,  Yasutoshi Okuno ,  Katsuyoshi Joukyu ,  Tetsuya Matsutani

发明人： Michikazu Matsumoto ,  Yasutoshi Okuno ,  Katsuyoshi Joukyu ,  Tetsuya Matsutani

IPC分类号： G01R31/08 ,  G01R31/28

CPC分类号： G01R31/2884 ,  G01R31/2853

摘要： A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device including test patterns capable of measuring a resistance variation component to be the resistance variation defect in each chip area or each shot area of the wafer, wherein the number of test patterns included in one chip area or one shot area is set so that it is possible to estimate the yield of the integrated circuit device.

摘要翻译： 一种电阻缺陷评估装置，设置在用于评估集成电路器件的部件中的电阻变化缺陷的晶片上，所述电阻缺陷评估装置包括能够测量每个芯片区域中的电阻变化分量的电阻变化分量作为电阻变化缺陷的测试图案， 晶片的每个照射区域，其中设置包括在一个芯片区域或一个照射区域中的测试图案的数量，使得可以估计集成电路器件的产量。