Time-Based Delay Line Analog Comparator

    公开(公告)号:US20180026648A1

    公开(公告)日:2018-01-25

    申请号:US15652710

    申请日:2017-07-18

    CPC classification number: H03M1/502 H03K5/14 H03K5/24 H03M1/1205

    Abstract: Embodiments of the present disclosure include voltage comparators. The voltage comparators may include a first input configured to receive a first analog voltage, a second input configured to receive a second analog voltage, a first digital delay line configured to propagate the first analog voltage through a first delay circuit and the second analog voltage through a second circuit, and an output circuit configured to provide a comparator output based upon whether values representing the first analog voltage or the second analog voltage propagated faster through the first digital delay line. The comparator output may be configured to identify whether the first analog voltage or the second analog voltage is greater.

    Time-based delay line analog comparator

    公开(公告)号:US10003353B2

    公开(公告)日:2018-06-19

    申请号:US15652710

    申请日:2017-07-18

    CPC classification number: H03M1/502 H03K5/14 H03K5/24 H03M1/1205

    Abstract: Embodiments of the present disclosure include voltage comparators. The voltage comparators may include a first input configured to receive a first analog voltage, a second input configured to receive a second analog voltage, a first digital delay line configured to propagate the first analog voltage through a first delay circuit and the second analog voltage through a second circuit, and an output circuit configured to provide a comparator output based upon whether values representing the first analog voltage or the second analog voltage propagated faster through the first digital delay line. The comparator output may be configured to identify whether the first analog voltage or the second analog voltage is greater.

    Time-based delay line analog-to-digital converter with variable resolution

    公开(公告)号:US10122375B2

    公开(公告)日:2018-11-06

    申请号:US15915796

    申请日:2018-03-08

    Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.

    Microcontroller with digital delay line analog-to-digital converter

    公开(公告)号:US10090850B2

    公开(公告)日:2018-10-02

    申请号:US15484965

    申请日:2017-04-11

    Abstract: Embodiments of the present disclosure include a microcontroller with a processor, memory, and peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.

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