公开(公告)号：US09923570B2

公开(公告)日：2018-03-20

申请号：US15485020

申请日：2017-04-11

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Neil Deutscher ,  Thomas S. Spohrer

IPC: H03M1/34 ,  H03M1/10 ,  H03K5/14 ,  H03K5/131 ,  H03K5/00

CPC classification number: H03M1/34 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03M1/007 ,  H03M1/1009 ,  H03M1/1028 ,  H03M1/1057 ,  H03M1/1071 ,  H03M1/18 ,  H03M1/38 ,  H03M1/502

Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.

公开(公告)号：US10122375B2

公开(公告)日：2018-11-06

申请号：US15915796

申请日：2018-03-08

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Neil Deutscher ,  Thomas S. Spohrer

IPC: H03M1/34 ,  H03K5/131 ,  H03K5/14 ,  H03M1/10 ,  H03M1/38 ,  H03M1/00 ,  H03M1/18 ,  H03K5/00 ,  H03M1/50

Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.

公开(公告)号：US20180198461A1

公开(公告)日：2018-07-12

申请号：US15915796

申请日：2018-03-08

Applicant: Microchip Technology Incorporated

Inventor： Bryan Kris ,  Neil Deutscher ,  Thomas S. Spohrer

IPC: H03M1/34 ,  H03M1/10 ,  H03K5/131 ,  H03K5/14 ,  H03K5/00

CPC classification number: H03M1/34 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03M1/007 ,  H03M1/1009 ,  H03M1/1028 ,  H03M1/1057 ,  H03M1/1071 ,  H03M1/18 ,  H03M1/38 ,  H03M1/502

Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.