公开(公告)号：US20230260565A1

公开(公告)日：2023-08-17

申请号：US17898737

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Edmund GIESKE ,  Sujeet AYYAPUREDDI ,  Yang LU ,  Amitava MAJUMDAR

IPC: G11C11/4078 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G11C11/40615 ,  G11C11/40618

Abstract: Practical, energy-efficient, and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The mitigation may be implemented on a per-bank basis. The memory media device may be DRAM.

公开(公告)号：US20230237152A1

公开(公告)日：2023-07-27

申请号：US17940785

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Sujeet AYYAPUREDDI ,  Tamara SCHMITZ ,  Edmund GIESKE ,  Nicolo IZZO ,  Markus H. GEIGER

IPC: G06F21/55 ,  G06F21/54

CPC classification number: G06F21/554 ,  G06F21/54 ,  G06F21/556

Abstract: A system and method detect a row hammer attack on the memory media device and generates a hardware interrupt based on the detection of the row hammer attack. This row hammer interrupt is communicated to an operating system of a host computing device, which in turn performs an interrupt service routine including generating a command to perform a row hammer mitigation operation. This command is provided to the memory controller which performs the row hammer mitigation operation in response to the command such as activating victim row(s) of the memory media device or throttling data traffic to the memory media device.

公开(公告)号：US20230352112A1

公开(公告)日：2023-11-02

申请号：US17730396

申请日：2022-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet AYYAPUREDDI

IPC: G11C29/42 ,  G11C29/18 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/18 ,  G11C29/1201

Abstract: Apparatuses, systems, and methods for per row error correct and scrub (pRECS) registers. A mode register may include a pRECS enable register, to enable a pRECS mode. When the prECS mode is enabled, pRECS information associated with each row may be collected which reflects a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row. A pRECS address register may specify a location in the memory array to store the pRECS information.

公开(公告)号：US20230282258A1

公开(公告)日：2023-09-07

申请号：US18160292

申请日：2023-01-26

Applicant: Micron Technology, Inc.

Inventor： Edmund GIESKE ,  Amitava MAJUMDAR ,  Cagdas DIRIK ,  Sujeet AYYAPUREDDI ,  Yang LU ,  Ameen D. AKEL ,  Danilo CARACCIO ,  Niccolo' IZZO ,  Elliott C. COOPER-BALIS ,  Markus H. GEIGER

IPC: G11C7/24 ,  G11C7/22 ,  G11C29/52

CPC classification number: G11C7/24 ,  G11C7/222 ,  G11C29/52

Abstract: Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

公开(公告)号：US20230238046A1

公开(公告)日：2023-07-27

申请号：US17941655

申请日：2022-09-09

Applicant: Micron Technology, Inc.

Inventor： Edmund GIESKE ,  Cagdas DIRIK ,  Robert M. WALKER ,  Sujeet AYYAPUREDDI ,  Niccolo IZZO ,  Markus GEIGER ,  Yang LU ,  Ameen AKEL ,  Elliott C. COOPER-BALIS ,  Danilo CARACCIO

IPC: G11C11/406 ,  G11C29/52

CPC classification number: G11C11/40618 ,  G11C11/40611 ,  G11C29/52

Abstract: An energy-efficient and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The reduction of the number of required counters is achieved by aliasing a plurality of rows that are being protected to each counter. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be DRAM.

公开(公告)号：US20230236735A1

公开(公告)日：2023-07-27

申请号：US17897813

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Sujeet AYYAPUREDDI ,  Yang LU ,  Edmund GIESKE ,  Cagdas DIRIK ,  Ameen D. AKEL ,  Elliott C. COOPER-BALIS ,  Amitava MAJUMDAR ,  Danilo CARACCIO ,  Robert M. WALKER

IPC: G06F3/06 ,  G06F11/07

CPC classification number: G06F3/0616 ,  G06F3/0673 ,  G06F3/0629 ,  G06F11/076 ,  G06F11/073

Abstract: Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).