公开(公告)号：US20230236968A1

公开(公告)日：2023-07-27

申请号：US17941558

申请日：2022-09-09

Applicant: Micron Technology, Inc.

Inventor： Edmund GIESKE ,  Cagdas DIRIK

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/1032

Abstract: A cache memory having a memory media device row activation-biased caching policy is described. The cache policies that are biased based on row activation counts include at least one of a cache line eviction policy which determines which cache lines are the most evictable from the cache memory, and cache line storage policy which determined which row data is allocated cache lines for storage. A memory controller including a row activation-biased cache memory is also described. The memory media device may be DRAM.

公开(公告)号：US20230282258A1

公开(公告)日：2023-09-07

申请号：US18160292

申请日：2023-01-26

Applicant: Micron Technology, Inc.

Inventor： Edmund GIESKE ,  Amitava MAJUMDAR ,  Cagdas DIRIK ,  Sujeet AYYAPUREDDI ,  Yang LU ,  Ameen D. AKEL ,  Danilo CARACCIO ,  Niccolo' IZZO ,  Elliott C. COOPER-BALIS ,  Markus H. GEIGER

IPC: G11C7/24 ,  G11C7/22 ,  G11C29/52

CPC classification number: G11C7/24 ,  G11C7/222 ,  G11C29/52

Abstract: Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

公开(公告)号：US20230238046A1

公开(公告)日：2023-07-27

申请号：US17941655

申请日：2022-09-09

Applicant: Micron Technology, Inc.

Inventor： Edmund GIESKE ,  Cagdas DIRIK ,  Robert M. WALKER ,  Sujeet AYYAPUREDDI ,  Niccolo IZZO ,  Markus GEIGER ,  Yang LU ,  Ameen AKEL ,  Elliott C. COOPER-BALIS ,  Danilo CARACCIO

IPC: G11C11/406 ,  G11C29/52

CPC classification number: G11C11/40618 ,  G11C11/40611 ,  G11C29/52

Abstract: An energy-efficient and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The reduction of the number of required counters is achieved by aliasing a plurality of rows that are being protected to each counter. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be DRAM.

公开(公告)号：US20230236739A1

公开(公告)日：2023-07-27

申请号：US17941551

申请日：2022-09-09

Applicant: Micron Technology, Inc.

Inventor： Edmund GIESKE ,  Cagdas DIRIK

IPC: G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0673 ,  G06F12/0802 ,  G06F2212/1032 ,  G06F2212/45

Abstract: A system comprising a row hammer mitigation circuitry and a cache memory that collaborate to mitigate row hammer attacks on a memory media device is described. The cache memory biases cache policy based on row access count information maintained by the row hammer mitigation circuit. The row hammer mitigation circuitry may be implemented in a memory controller. The memory media device may be DRAM. Corresponding methods are also described.

公开(公告)号：US20230236735A1

公开(公告)日：2023-07-27

申请号：US17897813

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Sujeet AYYAPUREDDI ,  Yang LU ,  Edmund GIESKE ,  Cagdas DIRIK ,  Ameen D. AKEL ,  Elliott C. COOPER-BALIS ,  Amitava MAJUMDAR ,  Danilo CARACCIO ,  Robert M. WALKER

IPC: G06F3/06 ,  G06F11/07

CPC classification number: G06F3/0616 ,  G06F3/0673 ,  G06F3/0629 ,  G06F11/076 ,  G06F11/073

Abstract: Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).