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公开(公告)号：US20230076362A1
公开(公告)日：2023-03-09
申请号：US17984929
申请日：2022-11-10
发明人： Michael G. Miller , Ashutosh Malshe , Gianni Stephen Alsasua , Renato Padilla, JR. , Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla , Harish Reddy Singidi
摘要： A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.
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公开(公告)号：US11436078B2
公开(公告)日：2022-09-06
申请号：US17228425
申请日：2021-04-12
发明人： Harish Reddy Singidi , Xiangang Luo , Jianmin Huang , Kishore Kumar Muchherla , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Sampath Ratnam
IPC分类号： G06F11/10 , G11C7/10 , G11C11/419 , G06F12/02
摘要： Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.
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公开(公告)号：US11334428B2
公开(公告)日：2022-05-17
申请号：US16989478
申请日：2020-08-10
发明人： Harish Reddy Singidi , Kishore Kumar Muchherla , Xiangang Luo , Vamsi Pavan Rayaprolu , Ashutosh Malshe
摘要： A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.
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公开(公告)号：US11238939B2
公开(公告)日：2022-02-01
申请号：US17158555
申请日：2021-01-26
发明人： Ting Luo , Kulachet Tanpairoj , Harish Reddy Singidi , Jianmin Huang , Preston Allen Thomson , Sebastien Andre Jean
IPC分类号： G11C11/34 , G11C16/16 , G11C16/04 , G11C16/08 , G11C11/56 , G11C16/34 , H01L27/11582 , H01L27/11556
摘要： Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.
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公开(公告)号：US20220019507A1
公开(公告)日：2022-01-20
申请号：US17492220
申请日：2021-10-01
发明人： Harish Reddy Singidi , Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla , Jianmin Huang , Xiangang Luo , Ashutosh Malshe
摘要： A variety of applications can include apparatus and/or methods to preemptively detect defect prone memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facililtate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US20210303394A1
公开(公告)日：2021-09-30
申请号：US17228425
申请日：2021-04-12
发明人： Harish Reddy Singidi , Xiangang Luo , Jianmin Huang , Kishore Kumar Muchherla , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Sampath Ratnam
IPC分类号： G06F11/10 , G11C7/10 , G11C11/419 , G06F12/02
摘要： Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.
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公开(公告)号：US11106530B2
公开(公告)日：2021-08-31
申请号：US16723836
申请日：2019-12-20
发明人： Chun Sum Yeung , Falgun G. Trivedi , Harish Reddy Singidi , Xiangang Luo , Preston Allen Thomson , Ting Luo , Jianmin Huang
IPC分类号： G06F11/10 , G06F12/02 , G06F12/0882 , G06F11/07
摘要： A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US20210151111A1
公开(公告)日：2021-05-20
申请号：US17158555
申请日：2021-01-26
发明人： Ting Luo , Kulachet Tanpairoj , Harish Reddy Singidi , Jianmin Huang , Preston Allen Thomson , Sebastien Andre Jean
摘要： Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.
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公开(公告)号：US10996867B2
公开(公告)日：2021-05-04
申请号：US16506372
申请日：2019-07-09
IPC分类号： G06F3/06 , G06F12/02 , G06F12/1009 , G06F12/1027
摘要： Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die of a NAND array of the NAND device. A set of partial super block candidates is also calculated. A partial superblock candidate is a superblock candidate that has at least one plane that has a bad block. A partial superblock use classification may then be obtained. Superblocks may be established for the NAND device by using members of the set of superblock candidates after removing the set of partial superblock candidates from the set of superblock candidates. Partial superblocks may then be established for classes of data in the NAND device according to the partial superblock use classification.
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公开(公告)号：US10930352B2
公开(公告)日：2021-02-23
申请号：US16601275
申请日：2019-10-14
发明人： Xiangang Luo , Jianmin Huang , Jung Sheng Hoei , Harish Reddy Singidi , Ting Luo , Ankit Vinod Vashi
摘要： Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.
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