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公开(公告)号：US11620074B2
公开(公告)日：2023-04-04
申请号：US17203474
申请日：2021-03-16
发明人： Kishore Kumar Muchherla , Devin M. Batutis , Xiangang Luo , Mustafa N. Kaynak , Peter Feeley , Sivagnanam Parthasarathy , Sampath Ratnam , Shane Nowell
摘要： A current memory access voltage distribution is measured for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device. The first voltage bin is associated with a first voltage offset. A current value for a reference voltage is determined based on the current memory access voltage distribution measured for the memory page. An amount of voltage shift for the memory page is determined based on the current value for the reference voltage a prior value for the reference voltage. The prior value for the reference voltage is associated with a prior memory access voltage distribution for the memory page. In response to a determination that the amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the plurality of voltage bins. The second voltage bin is associated with a second voltage offset.
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公开(公告)号：US11436078B2
公开(公告)日：2022-09-06
申请号：US17228425
申请日：2021-04-12
发明人： Harish Reddy Singidi , Xiangang Luo , Jianmin Huang , Kishore Kumar Muchherla , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Sampath Ratnam
IPC分类号： G06F11/10 , G11C7/10 , G11C11/419 , G06F12/02
摘要： Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.
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公开(公告)号：US20210303394A1
公开(公告)日：2021-09-30
申请号：US17228425
申请日：2021-04-12
发明人： Harish Reddy Singidi , Xiangang Luo , Jianmin Huang , Kishore Kumar Muchherla , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Sampath Ratnam
IPC分类号： G06F11/10 , G11C7/10 , G11C11/419 , G06F12/02
摘要： Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.
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4.发明授权公开(公告)号：US11024394B2
公开(公告)日：2021-06-01
申请号：US16844269
申请日：2020-04-09
发明人： Harish Singidi , Kishore Muchherla , Ashutosh Malshe , Vamsi Rayaprolu , Sampath Ratnam , Renato Padilla, Jr. , Michael Miller
摘要： A memory sub-system can be determined to be operating within a target operating characteristic based on a threshold success rate associated with error control operations using a particular parameter. Upon determining that the memory sub-system is operating within the target operating characteristic, a sticky read mode is entered by performing subsequent read operations using the particular parameter. It is determined that additional error control operations are triggered for at least a first threshold number of read operations using the particular parameter during the sticky read mode. Upon determining that the additional error control operations are triggered for at least the first threshold number of read operations using the particular parameter during the sticky read mode, the sticky read mode is exited by performing further read operations using a default parameter associated with the memory sub-system.
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公开(公告)号：US20200319827A1
公开(公告)日：2020-10-08
申请号：US16909503
申请日：2020-06-23
发明人： Gianni Stephen Alsasua , Karl D. Schuh , Ashutosh Malshe , Kishore Kumar Muchherla , Vamsi Pavan Rayaprolu , Sampath Ratnam , Harish Reddy Singidi , Renato Padilla, JR.
IPC分类号： G06F3/06 , G06F12/1009 , G11C16/34 , G11C16/26
摘要： Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
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6.发明申请公开(公告)号：US20200234775A1
公开(公告)日：2020-07-23
申请号：US16844269
申请日：2020-04-09
发明人： Harish Singidi , Kishore Muchherla , Ashutosh Malshe , Vamsi Rayaprolu , Sampath Ratnam , Renato Padilla, JR. , Michael Miller
摘要： A memory sub-system can be determined to be operating within a target operating characteristic based on a threshold success rate associated with error control operations using a particular parameter. Upon determining that the memory sub-system is operating within the target operating characteristic, a sticky read mode is entered by performing subsequent read operations using the particular parameter. It is determined that additional error control operations are triggered for at least a first threshold number of read operations using the particular parameter during the sticky read mode. Upon determining that the additional error control operations are triggered for at least the first threshold number of read operations using the particular parameter during the sticky read mode, the sticky read mode is exited by performing further read operations using a default parameter associated with the memory sub-system.
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公开(公告)号：US10691377B2
公开(公告)日：2020-06-23
申请号：US16138334
申请日：2018-09-21
发明人： Gianni Stephen Alsasua , Harish Reddy Singidi , Peter Sean Feeley , Ashutosh Malshe , Renato Padilla, Jr. , Kishore Kumar Muchherla , Sampath Ratnam
摘要： Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
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公开(公告)号：US20200160894A1
公开(公告)日：2020-05-21
申请号：US16749481
申请日：2020-01-22
发明人： Kishore Kumar Muchherla , Ashutosh Malshe , Harish Reddy Singidi , Gianni Stephen Alsasua , Gary F. Besinga , Sampath Ratnam , Peter Sean Feeley
摘要： A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US10579307B2
公开(公告)日：2020-03-03
申请号：US16566545
申请日：2019-09-10
发明人： Michael G. Miller , Kishore Kumar Muchherla , Harish Reddy Singidi , Sampath Ratnam , Renato Padilla, Jr. , Gary F. Besinga , Peter Sean Feeley
摘要： Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.
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公开(公告)号：US10366763B2
公开(公告)日：2019-07-30
申请号：US15799616
申请日：2017-10-31
发明人： Harish Singidi , Kishore Kumar Muchherla , Gianni Stephen Alsasua , Ashutosh Malshe , Sampath Ratnam , Gary F. Besinga , Michael G. Miller
摘要： Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
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