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公开(公告)号：US20230110545A1
公开(公告)日：2023-04-13
申请号：US18079843
申请日：2022-12-12
发明人： Kishore Kumar Muchherla , Harish R. Singidi , Vamsi Pavan Rayaprolu , Ashutosh Malshe , Sampath K. Ratnam
摘要： A request to perform a secure erase operation for a memory component can be received. A voltage level of a pass voltage that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied during a program operation to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can exceed the pass voltage applied to the unselected wordlines of the memory component during the read operation.
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公开(公告)号：US11615858B2
公开(公告)日：2023-03-28
申请号：US17341830
申请日：2021-06-08
IPC分类号： G06F11/10 , G06F11/34 , G06F16/11 , G06F16/16 , G06F16/17 , G06F3/06 , G06F12/02 , G11C16/34 , G11C16/10 , G11C16/16 , G06F12/0891 , G11C16/26
摘要： A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.
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公开(公告)号：US11561722B2
公开(公告)日：2023-01-24
申请号：US17002374
申请日：2020-08-25
摘要： A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device, to store host data in the page of the data unit. The processing device further generates a parity page for the host data stored in the page of the data unit and adds the parity page to parity data stored at a parity data storage location. Responsive to determining that a first size of the stored parity data satisfies a first condition, the processing device initiates execution of a compression algorithm to compress the stored parity data. Responsive to determining that a second size of the parity data resulting from the execution of the compression algorithm satisfies a second condition, the processing device performs a scan operation to release at least a subset of the stored parity data.
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公开(公告)号：US20220383962A1
公开(公告)日：2022-12-01
申请号：US17886884
申请日：2022-08-12
发明人： Kishore Kumar Muchherla , Harish R. Singidi , Renato C. Padilla , Vamsi Pavan Rayaprolu , Ashutosh Malshe , Sampath K. Ratnam
摘要： A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.
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公开(公告)号：US20220343984A1
公开(公告)日：2022-10-27
申请号：US17859926
申请日：2022-07-07
摘要： A method includes determining a first valid translation unit count (VTC) for a first block of memory cells, determining a second VTC for a second block of memory cells when the first VTC is below a VTC threshold corresponding to performance of a memory management operation, consolidating the first VTC and the second VTC when the consolidated first VTC and the second VTC equal or exceed the VTC threshold corresponding to the performance of the memory management operation, and executing the memory management operation utilizing the consolidated first VTC and the second VTC.
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公开(公告)号：US20220334756A1
公开(公告)日：2022-10-20
申请号：US17235216
申请日：2021-04-20
发明人： Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla , Ashutosh Malshe , Giuseppina Puzzilli , Saeed Sharifi Tehrani
IPC分类号： G06F3/06
摘要： Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, receiving a read request to perform a read operation on a block of the memory device; determining whether an entry corresponding to the block is stored in a data structure associated with the memory device; responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device; resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since the read operation was performed on the block of the memory device; determining that the counter and the timer satisfy a first criterion; and responsive to determining that the counter and the timer satisfy the first criterion, removing the entry corresponding to the block from the data structure associated with the memory device.
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公开(公告)号：US20220310190A1
公开(公告)日：2022-09-29
申请号：US17212531
申请日：2021-03-25
发明人： Gary F. Besinga , Renato C. Padilla , Tawalin Opastrakoon , Sampath K. Ratnam , Michael G. Miller , Christopher M. Smitchger , Vamsi Pavan Rayaprolu , Ashutosh Malshe
摘要： A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.
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公开(公告)号：US11437111B2
公开(公告)日：2022-09-06
申请号：US17122758
申请日：2020-12-15
发明人： Jeffrey S. McNeil, Jr. , Karl D. Schuh , Vamsi Pavan Rayaprolu , Giuseppina Puzzilli , Kishore K. Muchherla , Gil Golov , Todd A. Marquart , Jiangang Wu , Niccolo' Righetti , Ashutosh Malshe
摘要： Instructions can be executed to adjust a trim at first intervals until a quantity of program/erase cycles (PEC) have occurred. The trim defines a valley width between data states. Instructions can be executed to adjust the trim at second intervals, greater than the first intervals, after the quantity of PEC have occurred.
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公开(公告)号：US11379122B2
公开(公告)日：2022-07-05
申请号：US17178976
申请日：2021-02-18
摘要： A set of memory cells in a data block of a memory component is sampled. A distribution statistic is generated for the data block based on a reliability statistic for each of the set of sampled memory cells. A determination is made based on the distribution statistic of whether the read disturb stress is uniformly or non-uniformly distributed across the data block. In response to a determination that the read disturb stress is non-uniformly distributed across the data block, a first subset of the data block is relocated to another data block of the memory component. The first subset of the data block is associated with a higher concentration of read disturb stress than other subsets of the data block.
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公开(公告)号：US20220199189A1
公开(公告)日：2022-06-23
申请号：US17393886
申请日：2021-08-04
摘要： Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).
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