公开(公告)号：US08610490B2

公开(公告)日：2013-12-17

申请号：US13849586

申请日：2013-03-25

Applicant: Micron Technology, Inc.

Inventor： Giulio G. Marotta ,  Carlo Musilli ,  Stefano Perugini ,  Alessandro Torsi ,  Tommaso Vali

IPC: H03K17/687

CPC classification number: G11C7/12 ,  H03K3/35613 ,  H03K19/018528

Abstract: Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.

Abstract translation: 公开了电压开关，存储器件，存储器系统和用于切换的方法。 一个这样的电压开关使用串联耦合的一对开关电路，每个开关电路由电平移位电路驱动。 每个开关电路使用具有并联控制晶体管的一组串联耦合晶体管，其中每组中的晶体管数量可由每个晶体管的预期开关输入电压和最大允许电压降确定。 使能信号的特定状态的电压由电平移位电路移动到开关输入电压。 使能信号的特定状态使电压开关导通，使得开关输出电压基本上等于开关输入电压。

公开(公告)号：US20200160892A1

公开(公告)日：2020-05-21

申请号：US16774182

申请日：2020-01-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Agostino Macerola ,  Marco-Domenico Tiburzi ,  Stefano Perugini

IPC: G11C5/14 ,  G06F1/3203 ,  G06F1/3234 ,  G05F3/16 ,  G11C16/30

Abstract: Charge pumps of integrated circuit devices might include an input configured to receive an internally-generated first voltage level, an output, and a plurality of stages between its input and output. A particular stage might include a voltage isolation device, a voltage driver, and a capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to the voltage isolation device. The voltage driver might be responsive to a clock signal and to a voltage level of the output of the voltage driver to selectively connect the output of the voltage driver to either a first voltage node configured to receive the first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, or a third voltage node configured to receive a third voltage level lower than the second voltage level

公开(公告)号：US20190051334A1

公开(公告)日：2019-02-14

申请号：US16118724

申请日：2018-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Agostino Macerola ,  Marco-Domenico Tiburzi ,  Stefano Perugini

IPC: G11C5/14 ,  G05F3/16 ,  G06F1/32

Abstract: Voltage generation circuits include a stage including a voltage driver having inputs connected to respective voltage nodes and a clock signal, and a stage capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to a voltage isolation device. The voltage driver might be configured to connect its output to receive a first voltage when the clock signal has a particular logic level and a voltage level of its output is less than a threshold, to connect its output to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of its output is greater than the threshold, and to connect its output to receive a third voltage less than the first voltage when the clock signal has a different logic level.

公开(公告)号：US10515669B2

公开(公告)日：2019-12-24

申请号：US16118724

申请日：2018-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Agostino Macerola ,  Marco-Domenico Tiburzi ,  Stefano Perugini

IPC: G11C5/14 ,  G05F3/16 ,  G06F1/3203 ,  G06F1/3234 ,  G11C16/30 ,  G11C16/04

Abstract: Voltage generation circuits include a stage including a voltage driver having inputs connected to respective voltage nodes and a clock signal, and a stage capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to a voltage isolation device. The voltage driver might be configured to connect its output to receive a first voltage when the clock signal has a particular logic level and a voltage level of its output is less than a threshold, to connect its output to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of its output is greater than the threshold, and to connect its output to receive a third voltage less than the first voltage when the clock signal has a different logic level.

公开(公告)号：US10157644B1

公开(公告)日：2018-12-18

申请号：US15671317

申请日：2017-08-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Agostino Macerola ,  Marco-Domenico Tiburzi ,  Stefano Perugini

IPC: G11C5/14 ,  G06F1/32 ,  G05F3/16

Abstract: Methods of operating a voltage generation circuit, and apparatus configured to perform such methods, include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the voltage driver output to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of the voltage driver output is less than a threshold, connecting the voltage driver output to a second voltage node configured to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of the voltage driver output is greater than the threshold, and connecting the voltage driver output to a third voltage node configured to receive a third voltage less than the first voltage when the clock signal has a different logic level.

公开(公告)号：US11715502B2

公开(公告)日：2023-08-01

申请号：US16774182

申请日：2020-01-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Agostino Macerola ,  Marco-Domenico Tiburzi ,  Stefano Perugini

IPC: G11C5/14 ,  G06F1/3234 ,  G05F3/16 ,  G06F1/3203 ,  G11C16/30 ,  G11C16/04

CPC classification number: G11C5/145 ,  G05F3/16 ,  G06F1/3203 ,  G06F1/3275 ,  G11C5/147 ,  G11C16/30 ,  G11C16/0458 ,  G11C16/0483

Abstract: Charge pumps of integrated circuit devices might include an input configured to receive an internally-generated first voltage level, an output, and a plurality of stages between its input and output. A particular stage might include a voltage isolation device, a voltage driver, and a capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to the voltage isolation device. The voltage driver might be responsive to a clock signal and to a voltage level of the output of the voltage driver to selectively connect the output of the voltage driver to either a first voltage node configured to receive the first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, or a third voltage node configured to receive a third voltage level lower than the second voltage level.

公开(公告)号：US10573353B2

公开(公告)日：2020-02-25

申请号：US16118691

申请日：2018-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Agostino Marcerola ,  Marco-Domenico Tiburzi ,  Stefano Perugini

IPC: G11C5/14 ,  G06F1/3203 ,  G06F1/3234 ,  G05F3/16

Abstract: Methods of operating a voltage generation circuit include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the output of the voltage driver to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of an output of the voltage driver is less than a threshold, connecting the output of the voltage driver to a second voltage node configured to receive a second voltage, greater than the first voltage, when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is greater than the threshold, and connecting the output of the voltage driver to a third voltage node configured to receive a third voltage, less than the first voltage, when the clock signal has a different logic level.

公开(公告)号：US20190051333A1

公开(公告)日：2019-02-14

申请号：US16118691

申请日：2018-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Agostino Macerola ,  Marco-Domenico Tiburzi ,  Stefano Perugini

IPC: G11C5/14 ,  G05F3/16 ,  G06F1/32

Abstract: Methods of operating a voltage generation circuit include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the output of the voltage driver to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of an output of the voltage driver is less than a threshold, connecting the output of the voltage driver to a second voltage node configured to receive a second voltage, greater than the first voltage, when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is greater than the threshold, and connecting the output of the voltage driver to a third voltage node configured to receive a third voltage, less than the first voltage, when the clock signal has a different logic level.