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公开(公告)号：US11704047B2
公开(公告)日：2023-07-18
申请号：US17536465
申请日：2021-11-29
IPC分类号： G06F3/06
CPC分类号： G06F3/0653 , G06F3/0604 , G06F3/0673
摘要： A system includes a memory array, a thermometer, and control logic, operatively coupled with the memory array and the thermometer, to perform operations including causing the thermometer to obtain a first temperature result, monitoring a time since obtaining the first temperature result, determining whether the time satisfies a threshold time condition, in response to determining that the time satisfies the threshold time condition, causing the thermometer to obtain a second temperature result from an automatic temperature reading, determining a difference between the second temperature result and a previously stored temperature result, and filtering the second temperature result based on the difference to obtain a new stored temperature result.
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公开(公告)号：US20190051333A1
公开(公告)日：2019-02-14
申请号：US16118691
申请日：2018-08-31
摘要： Methods of operating a voltage generation circuit include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the output of the voltage driver to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of an output of the voltage driver is less than a threshold, connecting the output of the voltage driver to a second voltage node configured to receive a second voltage, greater than the first voltage, when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is greater than the threshold, and connecting the output of the voltage driver to a third voltage node configured to receive a third voltage, less than the first voltage, when the clock signal has a different logic level.
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公开(公告)号：US20160371335A1
公开(公告)日：2016-12-22
申请号：US15253965
申请日：2016-09-01
发明人： Luca De Santis , Giulio G. Marotta , Marco-Domenico Tiburzi , Tommaso Vali , Frankie F. Roohparvar , Agostino Macerola
IPC分类号： G06F17/30 , G11C15/04 , G06F12/0802 , G11C29/50 , G06F7/20
CPC分类号： G06F17/30495 , G06F3/0628 , G06F7/20 , G06F12/0802 , G06F2212/1021 , G06F2212/608 , G11C7/1006 , G11C15/046 , G11C16/0483 , G11C16/06 , G11C29/50004 , G11C29/50016
摘要： Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.
摘要翻译： 用于促进图案匹配并具有存储器单元阵列的存储器件，用于存储关键字的表示的多个键寄存器和多个复用器，多个多路复用器的每个复用器用于从一个或多个多路复用器中选择一个位的表示 多个密钥寄存器的密钥寄存器与存储在存储器单元阵列中的数据进行比较。
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公开(公告)号：US20140126295A1
公开(公告)日：2014-05-08
申请号：US14070911
申请日：2013-11-04
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/349
摘要： Apparatuses and methods for reprogramming memory cells are described. One or more methods for memory cell operation includes programming a number of memory cells such that each of the number of memory cells are at either a first program state or a second program state, the second program state having a first program verify voltage associated therewith; and reprogramming the number of memory cells such that at least one of the number of memory cells is reprogrammed to a third program state having a second program verify voltage associated therewith, wherein those of the number of memory cells having a threshold voltage less than the second program verify voltage represent a same data value.
摘要翻译： 描述用于重新编程存储器单元的装置和方法。 用于存储器单元操作的一种或多种方法包括编程多个存储器单元，使得多个存储器单元中的每一个处于第一编程状态或第二编程状态，第二编程状态具有与其相关联的第一编程验证电压; 并且重新编程存储器单元的数量，使得多个存储器单元中的至少一个被重新编程到具有与其相关联的第二编程验证电压的第三编程状态，其中存储器单元的数量的阈值电压小于第二个 程序验证电压表示相同的数据值。
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公开(公告)号：US20220405002A1
公开(公告)日：2022-12-22
申请号：US17536465
申请日：2021-11-29
摘要： A system includes a memory array, a thermometer, and control logic, operatively coupled with the memory array and the thermometer, to perform operations including causing the thermometer to obtain a first temperature result, monitoring a time since obtaining the first temperature result, determining whether the time satisfies a threshold time condition, in response to determining that the time satisfies the threshold time condition, causing the thermometer to obtain a second temperature result from an automatic temperature reading, determining a difference between the second temperature result and a previously stored temperature result, and filtering the second temperature result based on the difference to obtain a new stored temperature result.
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公开(公告)号：US10089359B2
公开(公告)日：2018-10-02
申请号：US15253965
申请日：2016-09-01
发明人： Luca De Santis , Giulio G. Marotta , Marco-Domenico Tiburzi , Tommaso Vali , Frankie F. Roohparvar , Agostino Macerola
IPC分类号： G06F11/263 , G06F17/30 , G06F3/06 , G11C16/06 , G11C7/10 , G11C15/04 , G11C16/04 , G06F7/20 , G06F12/0802 , G11C29/50
摘要： Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.
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公开(公告)号：US20240321368A1
公开(公告)日：2024-09-26
申请号：US18671835
申请日：2024-05-22
发明人： Tommaso Vali , Agostino Macerola
CPC分类号： G11C16/3459 , G11C16/102 , G11C16/3404
摘要： A memory device includes a memory array comprising a plurality of wordlines, and control logic, operatively coupled with the memory array. The control logic causes a measurement programming pulse to be sequentially applied to each of the plurality of wordlines of the memory array and determines respective threshold voltages stored in a number of memory cells associated with each of the plurality of wordlines. The control logic further determines a difference in the respective threshold voltages based on a location of the number of memory cells within each wordline and determines a respective resistance-capacitance (RC) time constant for each of the plurality of wordlines in view of the difference in the respective threshold voltages.
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公开(公告)号：US12001233B2
公开(公告)日：2024-06-04
申请号：US17684909
申请日：2022-03-02
发明人： Agostino Macerola
摘要： An apparatus includes a voltage regulator coupled with a first voltage source, which supplies core memory circuitry. A first transistor is coupled between an output of the voltage regulator and input/output (I/O) circuitry. A second transistor is coupled between a second voltage source and the I/O circuitry, the second voltage source to power a set of I/O buffers. Control logic coupled with gates of the first and second transistors is to perform operations including: causing the second transistor to be activated to permit current to flow from the second voltage source to the I/O circuitry; in response to detecting a current draw from the I/O circuitry that satisfies a first threshold criterion, causing the first transistor to be activated; and causing the second transistor to be deactivated over a time interval during which the I/O circuitry is powered by the first voltage source and the second voltage source.
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公开(公告)号：US20230111614A1
公开(公告)日：2023-04-13
申请号：US17684956
申请日：2022-03-02
发明人： Agostino Macerola , Gianni Rea
摘要： A memory device includes an array of memory cells, a diode having a threshold voltage that changes with temperature, an analog-to-digital converter (ADC), and a pulse generator. The ADC includes a voltage comparator having a positive terminal coupled with the diode. The ADC further includes a first capacitor coupled between a negative terminal of the voltage comparator and ground, and a second capacitor selectively coupled between the first capacitor and a voltage reference node. The second capacitor has a smaller capacitance than that of the first capacitor. The pulse generator is coupled with the ADC and generates pulses. The pulses cause the first capacitor to connect to the second capacitor and equalize charge between the first capacitor and the second capacitor. An inverted signal of the pulses causes the second capacitor to be coupled with the voltage reference node to pre-charge the first capacitor.
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公开(公告)号：US20220390972A1
公开(公告)日：2022-12-08
申请号：US17684909
申请日：2022-03-02
发明人： Agostino Macerola
摘要： An apparatus includes a voltage regulator coupled with a first voltage source, which supplies core memory circuitry. A first transistor is coupled between an output of the voltage regulator and input/output (I/O) circuitry. A second transistor is coupled between a second voltage source and the I/O circuitry, the second voltage source to power a set of I/O buffers. Control logic coupled with gates of the first and second transistors is to perform operations including: causing the second transistor to be activated to permit current to flow from the second voltage source to the I/O circuitry; in response to detecting a current draw from the I/O circuitry that satisfies a first threshold criterion, causing the first transistor to be activated; and causing the second transistor to be deactivated over a time interval during which the I/O circuitry is powered by the first voltage source and the second voltage source.
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