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1.发明授权公开(公告)号：US06794250B2
公开(公告)日：2004-09-21
申请号：US10449296
申请日：2003-05-29
IPC分类号： H01L218247
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/42336 , H01L29/7881
摘要： A vertical split gate flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, a tunnel layer, a first doping region, and a second doping region. The floating gate is disposed in the lower portion of the trench and insulated from the adjacent substrate by a floating gate oxide layer. The control gate is disposed over the floating gate and insulated from the adjacent substrate by a control gate oxide layer. The inter-gate dielectric layer is disposed between the floating gate and the control gate for insulation of the floating gate and the control gaze. The first doping region is formed in the substrate adjacent to the control gate and the second doping region is formed in the substrate below the first doping region and adjacent to the control gate to serve as source and drain regions with the first doping region.
摘要翻译： 垂直分闸门闪存单元。 存储单元包括衬底，浮置栅极，控制栅极，隧道层，第一掺杂区域和第二掺杂区域。 浮动栅极设置在沟槽的下部，并通过浮栅氧化层与相邻衬底绝缘。 控制栅极设置在浮置栅极上并通过控制栅极氧化物层与相邻衬底绝缘。 栅极间电介质层设置在浮置栅极和控制栅极之间，用于浮动栅极和控制注视的绝缘。 第一掺杂区域形成在与控制栅极相邻的衬底中，并且第二掺杂区域形成在第一掺杂区域下方的衬底中并且与控制栅极相邻，以用作具有第一掺杂区域的源极和漏极区域。
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2.发明授权公开(公告)号：US06800895B2
公开(公告)日：2004-10-05
申请号：US10272176
申请日：2002-10-15
IPC分类号： H01L29788
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/42336 , H01L29/7881
摘要： A vertical split gate flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, a tunnel layer, a first doping region, and a second doping region. The floating gate is disposed in the lower portion of the trench and insulated from the adjacent substrate by a floating gate oxide layer. The control gate is disposed over the floating gate and insulated from the adjacent substrate by a control gate oxide layer. The inter-gate dielectric layer is disposed between the floating gate and the control gate for insulation of the floating gate and the control gate. The first doping region is formed in the substrate adjacent to the control gate and the second doping region is formed in the substrate below the first doping region and adjacent to the floating gate to serve as source and drain regions with the first doping region.
摘要翻译： 垂直分闸门闪存单元。 存储单元包括衬底，浮置栅极，控制栅极，隧道层，第一掺杂区域和第二掺杂区域。 浮动栅极设置在沟槽的下部，并通过浮栅氧化层与相邻衬底绝缘。 控制栅极设置在浮置栅极上并通过控制栅极氧化物层与相邻衬底绝缘。 栅极间电介质层设置在浮置栅极和控制栅极之间，用于浮动栅极和控制栅极的绝缘。 第一掺杂区域形成在与控制栅极相邻的衬底中，并且第二掺杂区域形成在第一掺杂区域下方的衬底中并且与浮置栅极相邻，以用作具有第一掺杂区域的源极和漏极区域。
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3.发明授权Device and method for detecting alignment of deep trench capacitors and word lines in DRAM devices 有权用于检测DRAM器件中深沟槽电容器和字线的对准的装置和方法公开(公告)号：US06801462B2
公开(公告)日：2004-10-05
申请号：US10612857
申请日：2003-07-03
申请人： Ming Cheng Chang , Jeng-Ping Lin , Tie Jiang Wu
发明人： Ming Cheng Chang , Jeng-Ping Lin , Tie Jiang Wu
IPC分类号： G11C700
CPC分类号： H01L27/10894 , G11C11/401 , G11C29/02 , G11C29/025 , H01L22/34 , H01L27/10861 , H01L27/10873 , H01L27/10891 , H01L27/10897
摘要： A test device and method for detecting alignment of word lines and deep trench capacitors in DRAM devices. In the test device, parallel first and second bar-type deep trenches capacitors are disposed in the scribe line region. The first and second bar-type deep trenches capacitors extend to the first and second pairs of memory cells in the memory region adjacent to the first active area respectively. The first and second bar-type deep trenches capacitors are electrically coupled to bit line contacts of the first and second pairs of memory cells respectively. First and second transistors have sources coupled to the first and second bar-type deep trenches capacitors respectively. A first bit line contact is electrically coupled to drains of the first and second transistors.
摘要翻译： 用于检测DRAM器件中的字线和深沟槽电容器的对准的测试装置和方法。 在测试装置中，平行的第一和第二条形深沟槽电容器设置在划线区域中。 第一和第二条形深沟槽电容器分别延伸到与第一有效区域相邻的存储器区域中的第一和第二对存储单元。 第一和第二条形深沟槽电容器分别电耦合到第一和第二对存储器单元的位线触点。 第一和第二晶体管分别具有耦合到第一和第二条形深沟槽电容器的源极。 第一位线接触件电耦合到第一和第二晶体管的漏极。
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公开(公告)号：US06696717B2
公开(公告)日：2004-02-24
申请号：US10299431
申请日：2002-11-18
申请人： Ming Cheng Chang , Jeng-Ping Lin
发明人： Ming Cheng Chang , Jeng-Ping Lin
IPC分类号： H01L2972
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10891
摘要： A memory cell with a vertical transistor and a trench capacitor. The memory cell includes a substrate having a trench and a trench capacitor disposed in the lower trench. A control gate, with a p-type polysilicon germanium layer and an overlying p-type polysilicon layer, is disposed in the upper trench and insulated from the substrate. A first insulating layer is disposed between the trench capacitor and the control gate. A first doped region is formed in the substrate around the first insulating layer and a second doped region is formed in the substrate around the second conductive layer.
摘要翻译： 具有垂直晶体管和沟槽电容器的存储单元。 存储单元包括具有沟槽的衬底和设置在下沟槽中的沟槽电容器。 具有p型多晶硅锗层和上覆p型多晶硅层的控制栅极设置在上沟槽中并与衬底绝缘。 第一绝缘层设置在沟槽电容器和控制栅极之间。 第一掺杂区域形成在第一绝缘层周围的衬底中，并且第二掺杂区域形成在第二导电层周围的衬底中。
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公开(公告)号：US5315160A
公开(公告)日：1994-05-24
申请号：US851998
申请日：1992-03-13
申请人： Ming Cheng Chang
发明人： Ming Cheng Chang
CPC分类号： H05B39/09 , H05B41/44 , Y10T307/484
摘要： A sequentially shifting control circuit for extendible light strings which includes a main controller in one end, a backward signal-generating circuit in the other end and a plurality of bidirectional shifting control units therebetween. Each bidirectional shifting control unit has a plurality of lights connected thereto, thereby constituting and enabling an extendible light string to be sequentially flashed in a forward direction or a backward direction or in both directions simultaneously. Only three conductive lines are required: one for positive power, one for ground, and one for transmitting different control signals which are represented and distinguished by different voltage ranges, voltage levels, and waveform periods, and are mixed together according to a same signal (synchronous signal) to transmit.
摘要翻译： 一种用于可伸缩灯串的顺序移位控制电路，包括一端的主控制器，另一端的反向信号发生电路和它们之间的多个双向移位控制单元。 每个双向变速控制单元具有连接到其上的多个灯，从而构成并使得可延伸的光束在向前或向后的方向或两个方向上同时顺序地闪烁。 只需要三个导线：一个用于正功率，一个用于接地，一个用于发送由不同电压范围，电压电平和波形周期表示和区分的不同控制信号，并根据相同的信号混合在一起（ 同步信号）进行传输。
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公开(公告)号：USD425232S
公开(公告)日：2000-05-16
申请号：US99656
申请日：1999-01-25
申请人： Ming Cheng Chang
设计人： Ming Cheng Chang
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公开(公告)号：US08415728B2
公开(公告)日：2013-04-09
申请号：US12945423
申请日：2010-11-12
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/76229 , H01L27/10876 , H01L27/10891
摘要： A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.
摘要翻译： 存储器件包括台面结构和字线。 具有两个相对侧表面的台面结构包括至少一对源极/漏极区域和与其中形成的一对源极/漏极区域对应的至少一个沟道基极区域。 字线包括两个线性部分和至少一个互连部分。 每个线性部分在台面结构的相邻侧表面上延伸，邻近通道基底区域。 至少一个互连部分穿过台面结构，连接两个线性部分。
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公开(公告)号：US08426925B2
公开(公告)日：2013-04-23
申请号：US12945536
申请日：2010-11-12
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76224 , H01L27/10876 , H01L27/10891
摘要： A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.
摘要翻译： 存储器件包括多个隔离件和沟槽填料，沿方向交替排列，隔离件和沟槽填料之间的多个台面结构，以及各自覆盖相应台面的侧表面的多个字线。 在本发明的一个实施例中，在沟槽填料的方向上测量的宽度小于隔离层的宽度，每个台面结构包括至少一个成对的源极/漏极区域和对应于配对源极的至少一个沟道基极区域 /漏极区域，并且每个字线在台面结构的侧表面上，与相应的隔离相邻，并且被布置为与通道基底区域相邻。
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