公开(公告)号：US06794250B2

公开(公告)日：2004-09-21

申请号：US10449296

申请日：2003-05-29

Applicant: Ming Cheng Chang ,  Cheng-Chih Huang ,  Jeng-Ping Lin

Inventor： Ming Cheng Chang ,  Cheng-Chih Huang ,  Jeng-Ping Lin

IPC: H01L218247

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7881

Abstract: A vertical split gate flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, a tunnel layer, a first doping region, and a second doping region. The floating gate is disposed in the lower portion of the trench and insulated from the adjacent substrate by a floating gate oxide layer. The control gate is disposed over the floating gate and insulated from the adjacent substrate by a control gate oxide layer. The inter-gate dielectric layer is disposed between the floating gate and the control gate for insulation of the floating gate and the control gaze. The first doping region is formed in the substrate adjacent to the control gate and the second doping region is formed in the substrate below the first doping region and adjacent to the control gate to serve as source and drain regions with the first doping region.

Abstract translation: 垂直分闸门闪存单元。 存储单元包括衬底，浮置栅极，控制栅极，隧道层，第一掺杂区域和第二掺杂区域。 浮动栅极设置在沟槽的下部，并通过浮栅氧化层与相邻衬底绝缘。 控制栅极设置在浮置栅极上并通过控制栅极氧化物层与相邻衬底绝缘。 栅极间电介质层设置在浮置栅极和控制栅极之间，用于浮动栅极和控制注视的绝缘。 第一掺杂区域形成在与控制栅极相邻的衬底中，并且第二掺杂区域形成在第一掺杂区域下方的衬底中并且与控制栅极相邻，以用作具有第一掺杂区域的源极和漏极区域。

公开(公告)号：US20070152263A1

公开(公告)日：2007-07-05

申请号：US11687573

申请日：2007-03-16

Applicant: Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

Inventor： Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

IPC: H01L29/788

CPC classification number: H01L27/1087 ,  H01L27/10832 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66181

Abstract: A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.

Abstract translation: 用于布置深沟槽和有源区域的动态随机存取存储器（DRAM）单元布局及其制造方法。 有源区域包括两个垂直晶体管，一个常见的位线触点和两个深沟槽。 第一垂直晶体管形成在第一深沟槽与第一栅极导电线部分重叠的区域上。 第二垂直晶体管形成在第二深沟槽与第二栅极导电线部分重叠的区域上。

公开(公告)号：US07109094B2

公开(公告)日：2006-09-19

申请号：US10972506

申请日：2004-10-25

Applicant: Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

Inventor： Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A second lining layer is then formed on the doped first lining layer. Etching is then performed to remove parts of the first lining layer and the second lining layer so that the height of the first lining layer is lower than the second lining layer. A sacrificial layer is then formed on the pad layer and filling the trench. Diffusion is then carried out so that the doped ions in the first lining layer out-diffuse to the substrate and form diffuse regions outside the two bottom corners of the trench.

Abstract translation: 浅沟槽隔离及其STI结构中防止潜行的方法。 提供具有形成在其上的焊盘层和沟槽的半导体衬底，随后在沟槽的侧壁上形成掺杂的第一衬里层。 然后在掺杂的第一衬里层上形成第二衬里层。 然后进行蚀刻以去除第一衬里层和第二衬里层的部分，使得第一衬里层的高度低于第二衬里层。 然后在焊盘层上形成牺牲层并填充沟槽。 然后进行扩散，使得第一衬里层中的掺杂离子扩散到衬底并在沟槽的两个底角之外形成漫射区。

公开(公告)号：US06958521B2

公开(公告)日：2005-10-25

申请号：US10639419

申请日：2003-08-11

Applicant: Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

Inventor： Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

IPC: H01L21/762 ,  H01L29/00

CPC classification number: H01L21/76224

Abstract: Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A second lining layer is then formed on the doped first lining layer. Etching is then performed to remove parts of the first lining layer and the second lining layer so that the height of the first lining layer is lower than the second lining layer. A sacrificial layer is then formed on the pad layer and filling the trench. Diffusion is then carried out so that the doped ions in the first lining layer out-diffuse to the substrate and form diffuse regions outside the two bottom corners of the trench.

Abstract translation: 浅沟槽隔离及其STI结构中防止潜行的方法。 提供具有形成在其上的焊盘层和沟槽的半导体衬底，随后在沟槽的侧壁上形成掺杂的第一衬里层。 然后在掺杂的第一衬里层上形成第二衬里层。 然后进行蚀刻以去除第一衬里层和第二衬里层的部分，使得第一衬里层的高度低于第二衬里层。 然后在焊盘层上形成牺牲层并填充沟槽。 然后进行扩散，使得第一衬里层中的掺杂离子扩散到衬底并在沟槽的两个底角之外形成漫射区。

公开(公告)号：US06909136B2

公开(公告)日：2005-06-21

申请号：US10604344

申请日：2003-07-14

Applicant: Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Change-Rong Wu ,  Hui-Min Mao

Inventor： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Change-Rong Wu ,  Hui-Min Mao

IPC: H01L21/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10864 ,  H01L27/10832 ,  H01L29/66181 ,  H01L29/945

Abstract: A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

Abstract translation: 公开了一种新颖的沟槽电容器DRAM单元结构。 本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。 传输晶体管设置在有源区域岛的拐角处。 传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层 栅极导体条。 源极和漏极限定折叠通道。 沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。

公开(公告)号：US20050127469A1

公开(公告)日：2005-06-16

申请号：US10972506

申请日：2004-10-25

Applicant: Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

Inventor： Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

IPC: H01L21/762 ,  H01L21/20 ,  H01L21/76 ,  H01L29/00

CPC classification number: H01L21/76224

Abstract: Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A second lining layer is then formed on the doped first lining layer. Etching is then performed to remove parts of the first lining layer and the second lining layer so that the height of the first lining layer is lower than the second lining layer. A sacrificial layer is then formed on the pad layer and filling the trench. Diffusion is then carried out so that the doped ions in the first lining layer out-diffuse to the substrate and form diffuse regions outside the two bottom corners of the trench.

Abstract translation: 浅沟槽隔离及其STI结构中防止潜行的方法。 提供具有形成在其上的焊盘层和沟槽的半导体衬底，随后在沟槽的侧壁上形成掺杂的第一衬里层。 然后在掺杂的第一衬里层上形成第二衬里层。 然后进行蚀刻以去除第一衬里层和第二衬里层的部分，使得第一衬里层的高度低于第二衬里层。 然后在焊盘层上形成牺牲层并填充沟槽。 然后进行扩散，使得第一衬里层中的掺杂离子扩散到衬底并在沟槽的两个底角之外形成漫射区。

公开(公告)号：US20050012131A1

公开(公告)日：2005-01-20

申请号：US10604344

申请日：2003-07-14

Applicant: Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Chang-Rong Wu ,  Hui-Min Mao

Inventor： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Chang-Rong Wu ,  Hui-Min Mao

IPC: H01L21/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10864 ,  H01L27/10832 ,  H01L29/66181 ,  H01L29/945

Abstract: A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

Abstract translation: 公开了一种新颖的沟槽电容器DRAM单元结构。 本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。 传输晶体管设置在有源区域岛的拐角处。 传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层 栅极导体条。 源极和漏极限定折叠通道。 沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。

公开(公告)号：US20050045936A1

公开(公告)日：2005-03-03

申请号：US10761985

申请日：2004-01-21

Applicant: Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

Inventor： Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1087 ,  H01L27/10832 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66181

Abstract: A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.

公开(公告)号：US06800895B2

公开(公告)日：2004-10-05

申请号：US10272176

申请日：2002-10-15

Applicant: Ming Cheng Chang ,  Cheng-Chih Huang ,  Jeng-Ping Lin

Inventor： Ming Cheng Chang ,  Cheng-Chih Huang ,  Jeng-Ping Lin

IPC: H01L29788

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7881

Abstract: A vertical split gate flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, a tunnel layer, a first doping region, and a second doping region. The floating gate is disposed in the lower portion of the trench and insulated from the adjacent substrate by a floating gate oxide layer. The control gate is disposed over the floating gate and insulated from the adjacent substrate by a control gate oxide layer. The inter-gate dielectric layer is disposed between the floating gate and the control gate for insulation of the floating gate and the control gate. The first doping region is formed in the substrate adjacent to the control gate and the second doping region is formed in the substrate below the first doping region and adjacent to the floating gate to serve as source and drain regions with the first doping region.

Abstract translation: 垂直分闸门闪存单元。 存储单元包括衬底，浮置栅极，控制栅极，隧道层，第一掺杂区域和第二掺杂区域。 浮动栅极设置在沟槽的下部，并通过浮栅氧化层与相邻衬底绝缘。 控制栅极设置在浮置栅极上并通过控制栅极氧化物层与相邻衬底绝缘。 栅极间电介质层设置在浮置栅极和控制栅极之间，用于浮动栅极和控制栅极的绝缘。 第一掺杂区域形成在与控制栅极相邻的衬底中，并且第二掺杂区域形成在第一掺杂区域下方的衬底中并且与浮置栅极相邻，以用作具有第一掺杂区域的源极和漏极区域。

公开(公告)号：US06696717B2

公开(公告)日：2004-02-24

申请号：US10299431

申请日：2002-11-18

Applicant: Ming Cheng Chang ,  Jeng-Ping Lin

Inventor： Ming Cheng Chang ,  Jeng-Ping Lin

IPC: H01L2972

CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/10891

Abstract: A memory cell with a vertical transistor and a trench capacitor. The memory cell includes a substrate having a trench and a trench capacitor disposed in the lower trench. A control gate, with a p-type polysilicon germanium layer and an overlying p-type polysilicon layer, is disposed in the upper trench and insulated from the substrate. A first insulating layer is disposed between the trench capacitor and the control gate. A first doped region is formed in the substrate around the first insulating layer and a second doped region is formed in the substrate around the second conductive layer.

Abstract translation: 具有垂直晶体管和沟槽电容器的存储单元。 存储单元包括具有沟槽的衬底和设置在下沟槽中的沟槽电容器。 具有p型多晶硅锗层和上覆p型多晶硅层的控制栅极设置在上沟槽中并与衬底绝缘。 第一绝缘层设置在沟槽电容器和控制栅极之间。 第一掺杂区域形成在第一绝缘层周围的衬底中，并且第二掺杂区域形成在第二导电层周围的衬底中。