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    NON VOLATILE MEMORY CELLS INCLUDING A FILAMENT GROWTH LAYER AND METHODS OF FORMING THE SAME
    1.
    发明申请
    NON VOLATILE MEMORY CELLS INCLUDING A FILAMENT GROWTH LAYER AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20100123117A1

    公开(公告)日：2010-05-20

    申请号：US12273691

    申请日：2008-11-19

    申请人： Ming Sun ,  Xilin Peng ,  Haiwen Xi ,  Michael Xuefei Tang

    发明人： Ming Sun ,  Xilin Peng ,  Haiwen Xi ,  Michael Xuefei Tang

    IPC分类号： H01L45/00

    CPC分类号： H01L45/085 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

    摘要： A non volatile memory cell that includes a first electrode; a variable resistive layer disposed on the first electrode; a filament growth layer disposed on the variable resistive layer, the filament growth layer including dielectric material and metal atoms; and a second electrode. In other embodiments, a memory array is disclosed that includes a plurality of non volatile memory cells, each non volatile memory cell including a first electrode; a variable resistive layer disposed on the first electrode; a filament growth layer disposed on the variable resistive layer, the filament growth layer including clusters of a first electrically conductive atomic component interspersed in an oxidized second atomic component; and a second electrode; at least one word line; and at least one bit line, wherein the word line is orthogonal to the bit line and each of the plurality of non volatile memory cells are operatively coupled to a word line and a bit line. In still other embodiments, methods are disclosed that include forming a non volatile memory cell include forming a first electrode; forming a variable resistive layer on the first electrode; depositing a two phase alloy layer on the variable resistive layer; converting the two phase alloy layer to a filament growth layer; and depositing a second electrode on the filament growth layer, thereby forming a non volatile memory cell.

    NON VOLATILE MEMORY CELLS INCLUDING A FILAMENT GROWTH LAYER AND METHODS OF FORMING THE SAME
    2.
    发明申请
    NON VOLATILE MEMORY CELLS INCLUDING A FILAMENT GROWTH LAYER AND METHODS OF FORMING THE SAME 审中-公开
    非挥发性记忆细胞，包括纤维生长层及其形成方法

    公开(公告)号：US20100285633A1

    公开(公告)日：2010-11-11

    申请号：US12841212

    申请日：2010-07-22

    申请人： Ming Sun ,  Xilin Peng ,  Haiwen Xi ,  Michael Xuefei Tang

    发明人： Ming Sun ,  Xilin Peng ,  Haiwen Xi ,  Michael Xuefei Tang

    IPC分类号： H01L21/02

    CPC分类号： H01L45/085 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

    摘要： A non volatile memory cell that includes a first electrode; a variable resistive layer disposed on the first electrode; a filament growth layer disposed on the variable resistive layer, the filament growth layer including dielectric material and metal atoms; and a second electrode. In other embodiments, a memory array is disclosed that includes a plurality of non volatile memory cells, each non volatile memory cell including a first electrode; a variable resistive layer disposed on the first electrode; a filament growth layer disposed on the variable resistive layer, the filament growth layer including clusters of a first electrically conductive atomic component interspersed in an oxidized second atomic component; and a second electrode; at least one word line; and at least one bit line, wherein the word line is orthogonal to the bit line and each of the plurality of non volatile memory cells are operatively coupled to a word line and a bit line. In still other embodiments, methods are disclosed that include forming a non volatile memory cell include forming a first electrode; forming a variable resistive layer on the first electrode; depositing a two phase alloy layer on the variable resistive layer; converting the two phase alloy layer to a filament growth layer; and depositing a second electrode on the filament growth layer, thereby forming a non volatile memory cell.

    摘要翻译： 一种非易失性存储单元，包括第一电极; 设置在所述第一电极上的可变电阻层; 设置在可变电阻层上的长丝生长层，细丝生长层包括介电材料和金属原子; 和第二电极。 在其他实施例中，公开了一种存储器阵列，其包括多个非易失性存储器单元，每个非易失性存储单元包括第一电极; 设置在所述第一电极上的可变电阻层; 设置在可变电阻层上的长丝生长层，所述长丝生长层包括散布在氧化的第二原子组分中的第一导电原子组分的簇; 和第二电极; 至少一个字线; 以及至少一个位线，其中所述字线与所述位线正交，并且所述多个非易失性存储器单元中的每一个可操作地耦合到字线和位线。 在其他实施例中，公开了包括形成非易失性存储单元的方法，包括形成第一电极; 在所述第一电极上形成可变电阻层; 在可变电阻层上沉积两相合金层; 将两相合金层转变成长丝生长层; 以及在所述长丝生长层上沉积第二电极，由此形成非易失性存储单元。

    Memory with separate read and write paths
    4.
    发明授权
    Memory with separate read and write paths 有权
    内存具有单独的读写路径

    公开(公告)号：US08422278B2

    公开(公告)日：2013-04-16

    申请号：US12974679

    申请日：2010-12-21

    申请人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    发明人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    IPC分类号： G11C11/15

    CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.

    摘要翻译： 存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。 巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。 磁性隧道结数据单元电耦合在读取位线和读取源极线之间。 磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。 写入电流通过巨磁电阻单元，以在高电阻状态和低电阻状态之间切换巨磁电阻单元。 磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

    Memory with separate read and write paths
    6.
    发明授权
    Memory with separate read and write paths 有权
    内存具有单独的读写路径

    公开(公告)号：US08400823B2

    公开(公告)日：2013-03-19

    申请号：US12774016

    申请日：2010-05-05

    申请人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    发明人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    IPC分类号： G11C11/00

    CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.

    摘要翻译： 存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。 巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。 磁性隧道结数据单元电耦合在读取位线和读取源极线之间。 磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。 写入电流通过巨磁电阻单元，以将巨磁阻单元切换到高电阻状态和低电阻状态之间。 磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

    Semiconductor device with thermally coupled phase change layers
    8.
    发明授权
    Semiconductor device with thermally coupled phase change layers 有权
    具有热耦合相变层的半导体器件

    公开(公告)号：US07969771B2

    公开(公告)日：2011-06-28

    申请号：US12242620

    申请日：2008-09-30

    申请人： Haiwen Xi ,  Michael Xuefei Tang ,  Yuankai Zheng ,  Patrick Ryan

    发明人： Haiwen Xi ,  Michael Xuefei Tang ,  Yuankai Zheng ,  Patrick Ryan

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

    摘要： Various embodiments of the present invention are generally directed to an apparatus and method associated with a semiconductor device with thermally coupled phase change layers. The semiconductor device comprises a first phase change layer selectively configurable in a relatively low resistance crystalline phase and a relatively high resistance amorphous phase, and a second phase change layer thermally coupled to the first phase change layer. The second phase change layer is characterized as a metal-insulator transition material. A programming pulse is applied to the semiconductor device from a first electrode layer to a second electrode layer to provide the first phase change layer with a selected resistance.

    摘要翻译： 本发明的各种实施例通常涉及与具有热耦合相变层的半导体器件相关联的装置和方法。 半导体器件包括可选择性地配置在相对低电阻的结晶相和相对高电阻的非晶相中的第一相变层，以及热耦合到第一相变层的第二相变层。 第二相变层的特征在于金属 - 绝缘体过渡材料。 将编程脉冲从第一电极层施加到第二电极层，以向第一相变层提供选定的电阻。

    MEMORY WITH SEPARATE READ AND WRITE PATHS
    9.
    发明申请
    MEMORY WITH SEPARATE READ AND WRITE PATHS 有权
    具有单独读取和写入数据的存储器

    公开(公告)号：US20110090733A1

    公开(公告)日：2011-04-21

    申请号：US12974679

    申请日：2010-12-21

    申请人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    发明人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    IPC分类号： G11C11/15

    CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.

    摘要翻译： 存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。 巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。 磁性隧道结数据单元电耦合在读取位线和读取源极线之间。 磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。 写入电流通过巨磁电阻单元，以在高电阻状态和低电阻状态之间切换巨磁电阻单元。 磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

    Memory with separate read and write paths
    10.
    发明授权
    Memory with separate read and write paths 有权
    内存具有单独的读写路径

    公开(公告)号：US07881098B2

    公开(公告)日：2011-02-01

    申请号：US12198416

    申请日：2008-08-26

    申请人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    发明人： Haiwen Xi ,  Hongyue Liu ,  Michael Xuefei Tang ,  Antoine Khoueir ,  Song S. Xue

    IPC分类号： G11C11/00

    CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell.

    摘要翻译： 存储单元包括电耦合在写位线和写入源线之间的电磁耦合单元和电耦合在读取位线和读取源极线之间的磁性隧道结数据单元的巨磁电阻单元。 通过巨磁电阻单元的写入电流将巨磁阻单元切换到高电阻状态和低电阻状态之间。 磁隧道结数据单元被配置为通过与巨磁阻单元的静磁耦合在高电阻状态和低电阻状态之间切换。 磁隧道结数据单元由通过磁性隧道结数据单元的读取电流读取。