公开(公告)号：US06671153B1

公开(公告)日：2003-12-30

申请号：US09659788

申请日：2000-09-11

申请人： Ming-Dou Ker ,  Wen-Yu Lo ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Wen-Yu Lo ,  Hun-Hsien Chang

IPC分类号： A02H322

CPC分类号： H01L27/0262 ,  H01L27/0255

摘要： A diode string with very low leakage current is used in power supply ESD clamp circuits. By adding an CMOS-Controlled Lateral SCR device into the cascaded diode string, the leakage current of this new diode string with 6 cascaded diodes under 5 Volts (3.3 Volts) forward bias can be controlled below 2.1 (1.07) nA at a temperature of 125° C. in a 0.35 &mgr;m silicide CMOS process. The holding voltage of this design with the CMOS-Controlled Lateral SCR can be linearly adjusted by changing the number of the cascaded diodes in the diode string for the application among the power lines with different voltage levels. The ESD level of this ESD clamp circuit is greater than 8,000 Volts in the Human-Body-Model ESD test. The diodes string is suitable for portable or low-power CMOS Integrated Circuit (IC) devices.

摘要翻译： 在电源ESD钳位电路中使用具有非常低的漏电流的二极管串。 通过将CMOS控制的横向SCR器件添加到级联二极管串中，在具有5伏特（3.3伏）正向偏压的6个级联二极管的新型二极管串联的漏极电流可以在125℃的温度下控制在2.1（1.07）nA以下 在0.35毫米硅化物CMOS工艺中。 通过改变具有不同电压电平的电源线之间的应用的二极管串中的级联二极管的数量，可以通过CMOS控制横向SCR的这种设计的保持电压进行线性调整。 该ESD钳位电路的ESD电平在人体模型ESD测试中大于8,000伏特。 二极管串适用于便携式或低功耗CMOS集成电路（IC）设备。

公开(公告)号：US06885529B2

公开(公告)日：2005-04-26

申请号：US09942785

申请日：2001-08-31

申请人： Ming-Dou Ker ,  Hun-Hsien Chang ,  Wen-Tai Wang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang ,  Wen-Tai Wang

IPC分类号： H01L23/60 ,  H01L27/02 ,  H02H3/22 ,  H02H9/00

CPC分类号： H01L27/0251

摘要： An object of the present invention is to provide a charged-device model (CDM) electrostatic discharge (ESD) protection circuit for an integrated circuit (IC). The ESD protection circuit comprises an ESD clamp device and a functional component. The ESD clamp device is coupled to a pad and a substrate having a first conductivity type. Under normal power operation, the ESD clamp device is closed. The functional component is formed on the substrate and coupled to the pad. The functional component has a first well having the first conductivity type and an isolating region having a second conductivity type for isolating the first well from the substrate. Under normal power operation, the functional component transmits signals between the IC and an external linkage. During an CDM ESD event, the CDM charges accumulated in the substrate are discharged via the ESD clamp circuit. Hence, the functional component is protected.

摘要翻译： 本发明的目的是提供一种用于集成电路（IC）的充电装置模型（CDM）静电放电（ESD）保护电路。 ESD保护电路包括ESD钳位装置和功能部件。 ESD钳位装置耦合到具有第一导电类型的焊盘和衬底。 在正常的电源操作下，ESD钳位装置关闭。 功能部件形成在基板上并且耦合到焊盘。 功能部件具有第一导电类型的第一阱和具有第二导电类型的隔离区，用于将第一阱与衬底隔离。 在正常功率操作下，功能组件在IC和外部连接之间传输信号。 在CDM ESD事件期间，积累在衬底中的CDM电荷通过ESD钳位电路放电。 因此，功能组件受到保护。

公开(公告)号：US06249410B1

公开(公告)日：2001-06-19

申请号：US09378948

申请日：1999-08-23

申请人： Ming-Dou Ker ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang

IPC分类号： H02H322

CPC分类号： H02H9/046 ,  H01L27/0251 ,  H01L27/0266

摘要： An ESD protection circuit is connected to an integrated circuit to dissipate an electrostatic charge from an ESD source placed in contact with two terminals of the integrated circuit to prevent damage to the integrated circuits. The ESD protection circuit has a ESD shunting circuit for shunting the electrostatic charge from integrated circuit. The ESD shunting circuit has a first port connected to one terminal of the integrated circuit, a second port connected to another terminal of the integrated circuit, and a third port. The ESD protection circuit additionally has an ESD detection circuit. The ESD detection circuit has a first input port connected to the one terminal of the integrated circuit, a second input port connected to the other terminal of the integrated circuit, and an output port connected to the third port of the ESD shunting circuit. When the ESD detection circuit detects the presence of the electrostatic charge from the ESD source, the ESD detection circuit generates an excess voltage at the third port that will damage the ESD shunting circuit. Finally The ESD protection circuit has a voltage clamping circuit connected between the third port of the ESD shunting circuit and one of the terminals of the integrated circuit to prevent the generation of the excess voltage at the third port of the ESD shunting circuit.

摘要翻译： ESD保护电路连接到集成电路以从与集成电路的两个端子接触的ESD源消散静电电荷，以防止对集成电路的损坏。 ESD保护电路具有用于从集成电路分流静电电荷的ESD分流电路。 ESD分流电路具有连接到集成电路的一个端子的第一端口，连接到集成电路的另一端子的第二端口和第三端口。 ESD保护电路还具有ESD检测电路。 ESD检测电路具有连接到集成电路的一个端子的第一输入端口，连接到集成电路的另一个端子的第二输入端口和连接到ESD分流电路的第三端口的输出端口。 当ESD检测电路检测到来自ESD源的静电电荷的存在时，ESD检测电路在第三端口产生将损坏ESD分流电路的过电压。 最后，ESD保护电路具有连接在ESD分流电路的第三端口与集成电路的一个端子之间的电压钳位电路，以防止在ESD分流电路的第三端口处产生过电压。

公开(公告)号：US06765771B2

公开(公告)日：2004-07-20

申请号：US09887980

申请日：2001-06-22

申请人： Ming-Dou Ker ,  Hun-Hsien Chang ,  Wen-Tai Wang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang ,  Wen-Tai Wang

IPC分类号： H02H900

CPC分类号： H01L27/0262 ,  H01L29/7436 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection component with a deep-N-well structure in CMOS technology and the relevant circuit designs are proposed in this invention. The ESD protection component comprises a lateral silicon controlled rectifier (SCR) and a deep N-well. The SCR comprises a P-type layer, an N-type layer, a first N-well and a first P-well. The P-type layer is used as an anode of the SCR; the N-type layer is used as a cathode of the SCR; the first N-well is located between the P-type layer and the N-type layer and is contacted with the P-type layer; and the first P-well is contacted to the first N-well and the N-type layer. The deep N-well is located between the first P-well and the P-substrate, and is used to isolate the electric connection between the P-substrate and the first P-well. A plurality of these ESD protection components arbitrarily connected in series increases the total holding voltage of ESD protection circuit, thus preventing occurrences of latch-up.

摘要翻译： 本发明提出CMOS技术中具有深N阱结构的ESD保护元件及相关电路设计。 ESD保护组件包括侧向可控硅整流器（SCR）和深N阱。 SCR包括P型层，N型层，第一N阱和第一P阱。 P型层用作SCR的阳极; N型层用作SCR的阴极; 第一N阱位于P型层和N型层之间，并与P型层接触; 并且第一P阱与第一N阱和N型层接触。 深N阱位于第一P阱和P衬底之间，用于隔离P衬底和第一P阱之间的电连接。 串联任意连接的多个ESD保护元件增加了ESD保护电路的总保持电压，从而防止闩锁的发生。

公开(公告)号：US06576958B2

公开(公告)日：2003-06-10

申请号：US09836217

申请日：2001-04-18

申请人： Ming-Dou Ker ,  Hun-Hsien Chang ,  Wen-Tai Wang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang ,  Wen-Tai Wang

IPC分类号： H01L2362

CPC分类号： H01L27/0292 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

摘要： Novel PMOS-bound and NMOS-bound diodes for ESD protection, together with their application circuits, are disclosed in this invention. The PMOS-bound (or NMOS bound) diode has a PMOS (or an NMOS) structure. The source/drain region enclosed by the control gate of the PMOS (or NMOS) is used as an anode (or cathode) of the PMOS-bound (or NMOS-bound) diode. The base of the PMOS (or NMOS) is used as a cathode (or anode) of the PMOS-bound (or NMOS-bound) diode. The control gate prevents any shallow trench isolation region from forming beside the p-n junction of the PMOS-bound (or NMOS-bound) diode, such that the ESD sustaining level doesn't suffer from the formation of the STI regions. Furthermore, by ensuring proper bias to the control gate during an ESD event, the turn-on speed of the PMOS-bound or NMOS-bound diode can be increased, such that the overall ESD level of an IC chip is improved. By applying the PMOS-bound or NMOS-bound diode, ESD protection circuits for I/O buffer, power-rail ESD clamping circuits and whole-chip ESD protection systems are also provided.

公开(公告)号：US06388850B1

公开(公告)日：2002-05-14

申请号：US09376066

申请日：1999-08-17

申请人： Ming-Dou Ker ,  Chen-Chia Wang ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Chen-Chia Wang ,  Hun-Hsien Chang

IPC分类号： H02H900

CPC分类号： H01L27/0251 ,  H02H9/046

摘要： An apparatus of preventing integrated circuits from interfering by electrostatic-discharge (ESD), applied in an internal circuit and an input pad, both coupled with a first power line and a second power line, comprises a voltage clamp circuit and a voltage bias circuit. The voltage clamp circuit, with a transistor, connects to the second power line for clamping potential level through the voltage clamp circuit. The voltage bias circuit, with at least one diode coupled in series, connects to the voltage clamp circuit and the first power line for biasing the voltage clamp circuit to the second power line.

摘要翻译： 防止集成电路与施加在内部电路中的静电放电（ESD）干扰的装置和与第一电力线和第二电力线耦合的输入焊盘的装置包括电压钳位电路和电压偏置电路。 具有晶体管的电压钳位电路连接到第二电源线，用于通过电压钳位电路钳位电位电平。 具有串联耦合的至少一个二极管的电压偏置电路连接到电压钳位电路和用于将电压钳位电路偏压到第二电力线的第一电力线。

公开(公告)号：US06838734B2

公开(公告)日：2005-01-04

申请号：US10323422

申请日：2002-12-19

申请人： Ming-Dou Ker ,  Tung-Yang Chen ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Tung-Yang Chen ,  Hun-Hsien Chang

IPC分类号： H01L21/8222 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/02 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0266 ,  H01L29/7833

摘要： High-voltage-tolerant ESD protection devices (ESDPD) for deep-submicron CMOS process were activated between LDD implanting and forming sidewall spacers. ESD-Implant (ESDI) regions are located at the ESDPD, without covering the center region under the drain contact (DC). The ESDI LDD concentration and doping profile are deep to contain drain diffusion. Regions with the ESDI have a high junction breakdown voltage (JBV) and a low junction capacitance. After forming gate sidewall spacers, high doping concentration ions implanted into active D/S regions formed a shallower doping profile of the D/S diffusion. The drain has a JBV as without this ESDI, so the ESD current (ESDC) is discharged through the center junction region under the DC to bulk, far from the ESDPD surface channel region. The ESDPD sustains a high ESD level. In an original drain JBV of an MOS this ESDI method is unchanged, i.e. the same as that having no such ESDI, so it can be used in I/O circuits with high-voltage signals in the deep-submicron CMOS. The ESD level of the IO ESDPD improves. The ESD discharge current path in the MOS device structure improves the ESD level in the output buffer MOS. ESDI regions are located at the output MOS devices, without covering the region under the DC. Regions under the DC without this ESDI have an unchanged JBV, so the ESDC discharges through the junction region under the DC to bulk. The original drain JBV of the output MOS with this ESDI method is unchanged, which is still the same as that having no such ESDI, to be used in the I/O circuits with high-voltage (5V) input signals in the deep-submicron CMOS with 3.3V or 2.5V VDD. This applies to diodes, FOD and lateral BJT devices.

摘要翻译： 用于深亚微米CMOS工艺的高耐压ESD保护器件（ESDPD）在LDD注入和形成侧壁间隔件之间被激活。 ESD植入（ESDI）区域位于ESDPD处，而不覆盖漏极接触（DC）下的中心区域。 ESDI LDD浓度和掺杂分布深度包含漏极扩散。 具有ESDI的区域具有高结击穿电压（JBV）和低结电容。 在形成栅极侧壁间隔物之后，注入有源D / S区的高掺杂浓度离子形成D / S扩散的较浅掺杂分布。 漏极具有没有这种ESDI的JBV，因此ESD电流（ESDC）通过DC到DCDP的中心连接区域放电到远离ESDPD表面沟道区域。 ESDPD维持高ESD级别。 在MOS的原始漏极JBV中，ESDI方法不变，即与没有这样的ESDI相同，因此可以在深亚微米CMOS中使用具有高电压信号的I / O电路。 IO ESDPD的ESD级别提高。 MOS器件结构中的ESD放电电流路径提高了输出缓冲器MOS中的ESD电平。 ESDI区域位于输出MOS器件，不覆盖DC下的区域。 在没有这种ESDI的DC下的区域具有不变的JBV，因此ESDC通过DC下的结区域放电。 具有这种ESDI方法的输出MOS的原始漏极JBV与在深亚微米级中具有高电压（5V）输入信号的I / O电路中使用的不相同，与没有这样的ESDI相同。 具有3.3V或2.5V VDD的CMOS。 这适用于二极管，FOD和侧向BJT器件。

公开(公告)号：US06514839B1

公开(公告)日：2003-02-04

申请号：US09970825

申请日：2001-10-05

申请人： Ming-Dou Ker ,  Tung-Yang Chen ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Tung-Yang Chen ,  Hun-Hsien Chang

IPC分类号： H01L21425

CPC分类号： H01L21/823814 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0266 ,  H01L29/7833

摘要： An implanting method forms high-voltage-tolerant ESD protection devices (ESDPD) for deep-submicron CMOS process activated between LDD implanting and forming sidewall spacers. ESD-Implant (ESDI) regions are located at the ESDPD, without covering the center region under the drain contact (DC). The ESDI LDD concentration and doping profile are deep to contain drain diffusion. Regions with the ESDI have a high junction breakdown voltage (JBV) and a low junction capacitance. After forming gate sidewall spacers, implant high doping concentration ions into active D/S regions forming a shallower doping profile of the D/S diffusion. The drain has a JBV as without this ESDI, so the ESD current (ESDC) is discharged through the center junction region under the DC to bulk, far from the ESDPD surface channel region. The ESDPD sustains a high ESD level. The original drain JBV of an MOS with this ESDI method is unchanged, i.e. the same as that having no such ESDI, so it can be used in I/O circuits with high-voltage signals in the deep-submicron CMOS. The ESD level of the I/O ESDPD improves. This method applies to high-voltage-tolerant I/O pins in a deep-submicron CMOS. The ESD discharge current path in the MOS device structure improves the ESD level in the output buffer MOS. ESDI regions are located at the output MOS devices, without covering the region under the DC. The method has a LDD concentration, so regions with this ESDI have a higher JBV and a lower junction capacitance. Regions under the DC without this ESDI have an unchanged JBV, so the ESDC discharges through the junction region under the DC to bulk.

摘要翻译： 注入方法形成用于在LDD注入和形成侧壁间隔物之间​​激活的深亚微米CMOS工艺的高耐压ESD保护器件（ESDPD）。 ESD植入（ESDI）区域位于ESDPD处，而不覆盖漏极接触（DC）下的中心区域。 ESDI LDD浓度和掺杂分布深度包含漏极扩散。 具有ESDI的区域具有高结击穿电压（JBV）和低结电容。 在形成栅极侧壁间隔物之后，将高掺杂浓度离子注入到形成D / S扩散的较浅掺杂分布的有源D / S区域中。 漏极具有没有这种ESDI的JBV，因此ESD电流（ESDC）通过DC到DCDP的中心连接区域放电到远离ESDPD表面沟道区域。 ESDPD维持高ESD级别。 具有这种ESDI方法的MOS的原始漏极JBV不变，即与没有这样的ESDI相同，因此可以在深亚微米CMOS中使用具有高电压信号的I / O电路。 I / O ESDPD的ESD级别提高。 该方法适用于深亚微米CMOS中的高耐压I / O引脚。 MOS器件结构中的ESD放电电流路径提高了输出缓冲器MOS中的ESD电平。 ESDI区域位于输出MOS器件，不覆盖DC下的区域。 该方法具有LDD浓度，因此具有该ESDI的区域具有较高的JBV和较低的结电容。 在没有这种ESDI的DC下的区域具有不变的JBV，因此ESDC通过DC下的结区域放电。

公开(公告)号：US06444404B1

公开(公告)日：2002-09-03

申请号：US09635585

申请日：2000-08-09

申请人： Tung-Yang Chen ,  Ming-Dou Ker ,  Hun-Hsien Chang

发明人： Tung-Yang Chen ,  Ming-Dou Ker ,  Hun-Hsien Chang

IPC分类号： G03C500

CPC分类号： H01L21/823814 ,  H01L21/823835

摘要： A process for forming an implanted ESD region, and for forming metal silicide blocking regions, using the same photolithographic mask for definition of these regions, has been developed. The process features the formation of an implanted ESD region, defined by a photoresist shape which in turn had been formed via exposure of a negative photoresist layer, using a specific photolithographic mask. Metal silicide regions are subsequently formed on regions of a semiconductor substrate, exposed in openings in an insulator layer, with the openings in the insulator layer defined via a photoresist shape, which in turn had been formed via exposure of a positive photoresist layer, using the same photolithographic mask previously used for definition of the implanted ESD region. In this invention we use only one photolithographic mask in the CMOS process to fabricate an ESD device having ESD implanted and metal silicide blocking regions, which can sustain higher ESD stress.

摘要翻译： 已经开发了用于形成植入的ESD区域并且用于形成金属硅化物阻挡区域的方法，其使用相同的光刻掩模来定义这些区域。 该工艺特征在于形成植入的ESD区域，其由通过曝光负性光致抗蚀剂层而形成的光刻胶形状限定，使用特定的光刻掩模。 金属硅化物区域随后形成在半导体衬底的在绝缘体层的开口中暴露的区域上，绝缘体层中的开口经由光致抗蚀剂形状限定，光致抗蚀剂形状又通过曝光正性光致抗蚀剂层形成，使用 以前用于植入的ESD区域的定义的相同的光刻掩模。 在本发明中，我们在CMOS工艺中仅使用一个光刻掩模来制造具有ESD注入的ESD器件和可以承受更高ESD应力的金属硅化物阻挡区域。

公开(公告)号：US06008684A

公开(公告)日：1999-12-28

申请号：US735894

申请日：1996-10-23

申请人： Ming-Dou Ker ,  Hun-Hsien Chang

发明人： Ming-Dou Ker ,  Hun-Hsien Chang

IPC分类号： H03K17/567 ,  H03K19/003 ,  H03K19/017 ,  H03K19/098 ,  H03K17/687

CPC分类号： H03K19/098 ,  H03K17/567 ,  H03K19/00315 ,  H03K19/01721

摘要： An MOS-controlled, lateral SCR device including a semiconductor substrate of a first doping type; a first well region formed in the substrate and being of a second doping type which is different from the first doping type; a second well region formed in the substrate, being of the second doping type, and being spaced apart from the first well region so as to define an intermediate region separating the first and second well regions from each other; a first region formed within the first well region and extending into the intermediate region between the first and second well regions, the first region being of the second doping type; a second region formed within the second well region and extending into the intermediate region between the first and second well regions, the second region being of the second doping type; and a control gate bridging over the intermediate region between the first and second regions.

摘要翻译： 一种MOS控制的横向SCR器件，包括第一掺杂类型的半导体衬底; 形成在所述衬底中并且具有不同于所述第一掺杂类型的第二掺杂类型的第一阱区; 形成在所述衬底中的第二阱区，所述第二阱区具有第二掺杂型，并且与所述第一阱区间隔开，以便限定使所述第一阱区和所述第二阱区彼此分离的中间区; 第一区域，形成在第一阱区内并延伸到第一和第二阱区之间的中间区域，第一区域是第二掺杂型; 第二区域，形成在第二阱区域内并延伸到第一和第二阱区域之间的中间区域，第二区域是第二掺杂型; 以及跨越所述第一和第二区域之间的中间区域的控制栅极。