摘要:
An electrostatic discharge (ESD) protection device includes a substrate; a source region of a first conductivity type in the substrate; a drain region of the first conductivity type in the substrate; a gate electrode overlying the substrate between the source region and the drain region; and a core pocket doping region of the second conductivity type within the drain region. The core pocket doping region does not overlap with an edge of the drain region.
摘要:
A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region.
摘要:
A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region.
摘要:
An electrostatic discharge (ESD) protection device includes a substrate; a source region of a first conductivity type in the substrate; a drain region of the first conductivity type in the substrate; a gate electrode overlying the substrate between the source region and the drain region; and a core pocket doping region of the second conductivity type within the drain region. The core pocket doping region does not overlap with an edge of the drain region.
摘要:
A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region.
摘要:
An integrated circuit chip includes a substrate; a topmost metal layer over the substrate; a lower metal layer on or over the substrate and lower than the topmost metal layer; and at least one bonding pad in the lower metal layer.
摘要:
A semiconductor device structure includes a substrate having a transistor thereon; a multi-layer contact etching stop layer (CESL) structure covering the transistor, the multi-layer CESL structure comprising a first CESL and a second CESL; and a dielectric layer on the second CESL. The first CESL is made of a material different from that of the second CESL, and the second CESL is made of a material different from that of the dielectric layer.
摘要:
A capacitor structure is provided. The capacitor structure includes a plurality of first conductive lines paralleled disposed in a conductive layer on a substrate, wherein the first conductive lines are isolated to each other in the conductive layer and are grouped into a first electrode group and a second electrode group, an insulating layer formed on the first conductive lines and in the space between the first conductive lines, a second conductive line formed on the insulating layer electrically connected to the first conductive lines of the first electrode group, and a third conductive line formed on the insulating layer electrically connected to the first conductive lines of the second electrode group.
摘要:
An interconnection structure includes an inter-layer dielectric; a topmost copper metal layer inlaid into the inter-layer dielectric; an insulating layer disposed on the inter-layer dielectric and the topmost copper metal layer; a via opening in the insulating layer for exposing a top surface of the topmost copper metal layer, wherein the via opening consists of an inwardly tapered upper via portion and a lower via portion having a substantially vertical sidewall profile; and an aluminum layer filling into the via opening.
摘要:
A memory structure, a memory device and a manufacturing method thereof are provided. First, a substrate is provided and a dielectric layer is formed over the substrate. Then, a pattern is formed in the dielectric layer. An amorphous silicon layer is formed in the pattern and over the dielectric layer. The amorphous silicon layer is patterned to form an electrode over the pattern. Then, a spacer is formed on the sidewall of the electrode. A selective hemispherical grains (HSGS) layer is formed over the surface of the electrode and the surface of the spacer.