公开(公告)号：US08054708B2

公开(公告)日：2011-11-08

申请号：US12604116

申请日：2009-10-22

申请人： Mingun Park ,  Chanho Kim ,  Sangwon Hwang

发明人： Mingun Park ,  Chanho Kim ,  Sangwon Hwang

IPC分类号： G11C7/00

CPC分类号： G11C5/143 ,  G11C5/144

摘要： A power-on detector supplied with a power supply voltage from an external source and detects a variation of the power supply voltage. The operating method of the power-on detector comprises calculating the slope of the rise of power supply voltage from a first voltage to a second voltage higher than the first voltage; and calculating the expected time for the power supply voltage to reach a target voltage level, based on the calculated slope.

摘要翻译： 上电检测器由外部电源提供电源电压，并检测电源电压的变化。 上电检测器的操作方法包括计算电源电压从第一电压上升到高于第一电压的第二电压的斜率; 以及基于计算的斜率计算电源电压达到目标电压电平的预期时间。

公开(公告)号：US20100135099A1

公开(公告)日：2010-06-03

申请号：US12604116

申请日：2009-10-22

申请人： Mingun Park ,  Chanho Kim ,  Sangwon Hwang

发明人： Mingun Park ,  Chanho Kim ,  Sangwon Hwang

IPC分类号： G11C5/14 ,  G01R21/06

CPC分类号： G11C5/143 ,  G11C5/144

摘要： A power-on detector supplied with a power supply voltage from an external source and detects a variation of the power supply voltage. The operating method of the power-on detector comprises calculating the slope of the rise of power supply voltage from a first voltage to a second voltage higher than the first voltage; and calculating the expected time for the power supply voltage to reach a target voltage level, based on the calculated slope.

摘要翻译： 上电检测器由外部电源提供电源电压，并检测电源电压的变化。 上电检测器的操作方法包括计算电源电压从第一电压上升到高于第一电压的第二电压的斜率; 以及基于计算的斜率计算电源电压达到目标电压电平的预期时间。

公开(公告)号：US20100027332A1

公开(公告)日：2010-02-04

申请号：US12500867

申请日：2009-07-10

申请人： Jinwook Lee ,  Jinyub Lee ,  Sangwon Hwang

发明人： Jinwook Lee ,  Jinyub Lee ,  Sangwon Hwang

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3454

摘要： A method, device and system are provided for programming a flash memory device, the method including executing a bit line setup operation, and executing a channel pre-charge operation simultaneously with the bit line setup operation, the channel pre-charge operation including applying a channel pre-charge voltage to all word lines; and the device including a voltage generator disposed for providing each of a program voltage, a read voltage, a pass voltage, and a channel pre-charge voltage, a high-voltage switch connected to the voltage generator and disposed for switchably providing one of the program voltage, read voltage, pass voltage, or channel pre-charge voltage, and control logic connected to the high-voltage switch and disposed for simultaneously executing a bit line setup operation and a channel pre-charge operation, the channel pre-charge operation comprising controlling the high-voltage switch to apply the channel pre-charge voltage to both selected and unselected word lines of the device.

摘要翻译： 提供了一种用于对闪速存储器件进行编程的方法，装置和系统，所述方法包括执行位线设置操作，以及与位线设置操作同时执行通道预充电操作，所述通道预充电操作包括应用 通道预充电电压到所有字线; 并且所述装置包括被设置用于提供编程电压，读取电压，通过电压和通道预充电电压中的每一个的电压发生器，连接到电压发生器的高压开关，并且被设置用于可切换地提供 编程电压，读取电压，通过电压或通道预充电电压，以及连接到高压开关的控制逻辑，并被设置用于同时执行位线设置操作和通道预充电操作，通道预充电操作 包括控制所述高压开关以将所述通道预充电电压施加到所述器件的所选择的和未选择的字线。

公开(公告)号：US08054682B2

公开(公告)日：2011-11-08

申请号：US12460940

申请日：2009-07-27

申请人： Kyung-Min Kang ,  Sangwon Hwang ,  Jong-Nam Baek

发明人： Kyung-Min Kang ,  Sangwon Hwang ,  Jong-Nam Baek

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

摘要： A non-volatile memory device includes a cell array including a plurality of memory cells, a page buffer block controlling bitlines of the plurality of memory cells to program the memory cells to a first target state or a second target state, and a control logic configured to skip a verify operation for the memory cells programmed to the first target state and perform a verify operation for the memory cells programmed to the second target state during a second program loop when the memory cells programmed to the first target state are determined to be in a pass condition during a first program loop.

摘要翻译： 一种非易失性存储器件包括：包括多个存储器单元的单元阵列;控制所述多个存储器单元的位线以将所述存储器单元编程为第一目标状态或第二目标状态的页缓冲器块;以及配置 跳过编程为第一目标状态的存储单元的验证操作，并且当编程为第一目标状态的存储器单元被确定为处于第二目标状态时，在第二程序循环期间对编程为第二目标状态的存储单元执行验证操作 在第一个程序循环期间的通过条件。

公开(公告)号：US07881133B2

公开(公告)日：2011-02-01

申请号：US12003140

申请日：2007-12-20

申请人： Sangwon Hwang ,  Jong-Soo Lee

发明人： Sangwon Hwang ,  Jong-Soo Lee

IPC分类号： G11C29/00

CPC分类号： G11C11/5621 ,  G11C11/56 ,  G11C16/04 ,  G11C29/00 ,  G11C29/42 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/0411 ,  G11C2211/5641 ,  G11C2229/723 ,  H01L27/101 ,  H01L27/105 ,  H01L27/1052

摘要： One embodiment of the method includes determining a type of cells in a block of the flash memory if an error is detected in at least a portion of the block, and selectively changing one of a cell type indicator and a bad block indicator associated with the block based on the determined type of cells in the block. The cell type indicator indicates a type of the cells in the associated block, and the bad block indicator indicates whether the associated block is a usable block.

摘要翻译： 该方法的一个实施例包括：如果在块的至少一部分中检测到错误，则确定闪存的块中的小区的类型，并且选择性地改变与块相关联的小区类型指示符和坏块指示符之一 基于块中确定的细胞类型。 小区类型指示符指示相关块中的小区的类型，坏块指示符指示相关块是否是可用块。

公开(公告)号：US20100008151A1

公开(公告)日：2010-01-14

申请号：US12495546

申请日：2009-06-30

申请人： Sangwon Hwang

发明人： Sangwon Hwang

IPC分类号： G11C16/06 ,  G11C7/04

CPC分类号： G11C11/5628 ,  G06F11/1068 ,  G11C7/04 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： A nonvolatile memory device is operated by programming sample data in the memory device for verification using verify voltage levels derived from an ideal verify voltage Vv associated with a particular temperature range, performing read verify operations on the sample data using the verify voltage Vv associated with the temperature range; and determining a temperature compensation parameter Nc based on results of the read verify operations.

摘要翻译： 非易失性存储器件通过在存储器件中编程采样数据来进行操作，以使用从与特定温度范围相关联的理想验证电压Vv导出的验证电压电平进行验证，使用与该特定温度范围相关联的验证电压Vv对采样数据执行读取验证操作 温度范围; 以及基于读验证操作的结果来确定温度补偿参数Nc。

公开(公告)号：US08531879B2

公开(公告)日：2013-09-10

申请号：US13080197

申请日：2011-04-05

申请人： Sangwon Hwang ,  DongKyu Youn ,  Jong-Nam Baek ,  Su Chang Jeon

发明人： Sangwon Hwang ,  DongKyu Youn ,  Jong-Nam Baek ,  Su Chang Jeon

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427 ,  G11C2216/14

摘要： A semiconductor memory device including a flash memory that includes a page, wherein the page includes a plurality of memory cells connected to even bitlines and odd bitlines of the flash memory, and the memory cells are disposed in a plurality of sectors. The semiconductor memory device also includes a memory controller configured to provide the flash memory with a read address that identifies sectors to be read. The flash memory is configured to determine a sequence of even sensing and odd sensing based on the read address and perform the even sensing and the odd sensing according to the determined sequence. In addition, the flash memory is configured to sense data of at least one identified sector that includes memory cells connected to the even bitlines during the even sensing and sense data of at least one identified sector that includes memory cells connected to the odd bitlines during the odd sensing.

摘要翻译： 一种包括闪存的半导体存储器件，包括页面，其中所述页面包括连接到所述闪速存储器的偶数位线和奇数位线的多个存储单元，并且所述存储器单元设置在多个扇区中。 半导体存储器件还包括存储器控制器，其被配置为向闪速存储器提供识别要读取的扇区的读地址。 闪速存储器被配置为基于读取地址确定偶数检测和奇数检测的顺序，并根据确定的顺序执行偶检测和奇检测。 另外，闪速存储器被配置为感测至少一个识别的扇区的数据，该数据包括在偶数感测期间连接到偶位线的存储器单元的数据，并且感测至少一个所识别的扇区的数据，该数据包括连接到奇数位线的存储器单元 奇感。

公开(公告)号：US08174902B2

公开(公告)日：2012-05-08

申请号：US12500867

申请日：2009-07-10

申请人： Jinwook Lee ,  Jinyub Lee ,  Sangwon Hwang

发明人： Jinwook Lee ,  Jinyub Lee ,  Sangwon Hwang

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3454

摘要： A method, device and system are provided for programming a flash memory device, the method including executing a bit line setup operation, and executing a channel pre-charge operation simultaneously with the bit line setup operation, the channel pre-charge operation including applying a channel pre-charge voltage to all word lines; and the device including a voltage generator disposed for providing each of a program voltage, a read voltage, a pass voltage, and a channel pre-charge voltage, a high-voltage switch connected to the voltage generator and disposed for switchably providing one of the program voltage, read voltage, pass voltage, or channel pre-charge voltage, and control logic connected to the high-voltage switch and disposed for simultaneously executing a bit line setup operation and a channel pre-charge operation, the channel pre-charge operation comprising controlling the high-voltage switch to apply the channel pre-charge voltage to both selected and unselected word lines of the device.

摘要翻译： 提供了一种用于对闪速存储器件进行编程的方法，装置和系统，所述方法包括执行位线设置操作，以及与位线设置操作同时执行通道预充电操作，所述通道预充电操作包括应用 通道预充电电压到所有字线; 并且所述装置包括被设置用于提供编程电压，读取电压，通过电压和通道预充电电压中的每一个的电压发生器，连接到电压发生器的高压开关，并且被设置用于可切换地提供 编程电压，读取电压，通过电压或通道预充电电压，以及连接到高压开关的控制逻辑，并被设置用于同时执行位线设置操作和通道预充电操作，通道预充电操作 包括控制所述高压开关以将所述通道预充电电压施加到所述器件的所选择的和未选择的字线。

公开(公告)号：US07929350B2

公开(公告)日：2011-04-19

申请号：US12542882

申请日：2009-08-18

申请人： Sangwon Hwang

发明人： Sangwon Hwang

IPC分类号： G11C16/04

CPC分类号： G11C16/30 ,  G11C16/10 ,  G11C16/16

摘要： A nonvolatile memory device includes a memory cell array; a voltage generator configured to provide stepwise increasing step pulses for varying logic states of memory cells in the memory cell array; and control logic configured to adjust an initial voltage of the stepwise increasing step pulses according to the number of the stepwise increasing step pulses.

摘要翻译： 非易失性存储器件包括存储单元阵列; 电压发生器，被配置为提供逐步增加的步进脉冲，用于改变存储单元阵列中存​​储单元的逻辑状态; 以及控制逻辑，被配置为根据逐步增加的步进脉冲的数量来调节逐步增加的步进脉冲的初始电压。

公开(公告)号：US20100067306A1

公开(公告)日：2010-03-18

申请号：US12542882

申请日：2009-08-18

申请人： Sangwon Hwang

发明人： Sangwon Hwang

IPC分类号： G11C16/04

CPC分类号： G11C16/30 ,  G11C16/10 ,  G11C16/16

摘要： A nonvolatile memory device includes a memory cell array; a voltage generator configured to provide stepwise increasing step pulses for varying logic states of memory cells in the memory cell array; and control logic configured to adjust an initial voltage of the stepwise increasing step pulses according to the number of the stepwise increasing step pulses.

摘要翻译： 非易失性存储器件包括存储单元阵列; 电压发生器，被配置为提供逐步增加的步进脉冲，用于改变存储单元阵列中存​​储单元的逻辑状态; 以及控制逻辑，被配置为根据逐步增加的步进脉冲的数量来调节逐步增加的步进脉冲的初始电压。