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1.发明申请SEMICONDUCTOR DEVICES INCLUDING FIELD EFFECT TRANSISTORS AND METHODS OF FORMING THE SAME 有权包括场效应晶体管的半导体器件及其形成方法公开(公告)号：US20160141373A1
公开(公告)日：2016-05-19
申请号：US14823229
申请日：2015-08-11
申请人： Mirco Cantoro , Zhenhua Wu , Krishna Bhuwalka , Sangsu Kim , Shigenobu Maeda
发明人： Mirco Cantoro , Zhenhua Wu , Krishna Bhuwalka , Sangsu Kim , Shigenobu Maeda
IPC分类号： H01L29/267 , H01L29/10 , H01L27/088 , H01L29/78 , H01L29/06 , H01L27/092
CPC分类号： H01L29/267 , H01L21/02524 , H01L21/02538 , H01L21/823412 , H01L21/823807 , H01L21/823878 , H01L27/088 , H01L27/0886 , H01L27/092 , H01L27/0924 , H01L29/0642 , H01L29/1054 , H01L29/1079 , H01L29/1606 , H01L29/165
摘要： A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.
摘要翻译： 半导体器件包括设置在衬底上的有源图案和与有源图案交叉的栅电极。 有源图案包括衬底上的第一缓冲器图案，第一缓冲器图案上的沟道图案，第一缓冲器图案和沟道图案之间的掺杂图案，以及掺杂图案和沟道图案之间的第二缓冲图案。 掺杂图案包括注入杂质的石墨烯。
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公开(公告)号：US20140021532A1
公开(公告)日：2014-01-23
申请号：US13553405
申请日：2012-07-19
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66977 , B82Y10/00 , H01L29/0657 , H01L29/0676 , H01L29/068 , H01L29/0688 , H01L29/1037 , H01L29/1054 , H01L29/205 , H01L29/42372 , H01L29/66356 , H01L29/66439 , H01L29/66522 , H01L29/66666 , H01L29/7391 , H01L29/775 , H01L29/7827
摘要： Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.
摘要翻译： 除此之外，本文提供了用于形成垂直隧道场效应晶体管（FET）的一种或多种技术以及所产生的垂直隧道FET。 在一个实施例中，垂直隧道FET通过在第一类型的衬底区域上形成芯体形成，围绕围绕圆周的圆周形成第二类型沟道壳体，围绕围绕圆周的圆周形成栅极电介质，形成 围绕圆周大于芯圆周的栅电极，并且在第二类型沟槽壳体的一部分上形成第二类型区域，其中第二类型具有与第一类型的掺杂相反的掺杂。 以这种方式，能够进行线路隧道，从而为垂直隧道FET提供增强的隧道效率。
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公开(公告)号：US08916927B2
公开(公告)日：2014-12-23
申请号：US13553405
申请日：2012-07-19
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/66977 , B82Y10/00 , H01L29/0657 , H01L29/0676 , H01L29/068 , H01L29/0688 , H01L29/1037 , H01L29/1054 , H01L29/205 , H01L29/42372 , H01L29/66356 , H01L29/66439 , H01L29/66522 , H01L29/66666 , H01L29/7391 , H01L29/775 , H01L29/7827
摘要： Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.
摘要翻译： 除此之外，本文提供了用于形成垂直隧道场效应晶体管（FET）的一种或多种技术以及所产生的垂直隧道FET。 在一个实施例中，垂直隧道FET通过在第一类型的衬底区域上形成芯体形成，围绕围绕圆周的圆周形成第二类型沟道壳体，围绕围绕圆周的圆周形成栅极电介质，形成 围绕圆周大于芯圆周的栅电极，并且在第二类型沟槽壳体的一部分上形成第二类型区域，其中第二类型具有与第一类型的掺杂相反的掺杂。 以这种方式，能够进行线路隧道，从而为垂直隧道FET提供增强的隧道效率。
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