公开(公告)号：US20160141373A1

公开(公告)日：2016-05-19

申请号：US14823229

申请日：2015-08-11

申请人： Mirco Cantoro ,  Zhenhua Wu ,  Krishna Bhuwalka ,  Sangsu Kim ,  Shigenobu Maeda

发明人： Mirco Cantoro ,  Zhenhua Wu ,  Krishna Bhuwalka ,  Sangsu Kim ,  Shigenobu Maeda

IPC分类号： H01L29/267 ,  H01L29/10 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092

CPC分类号： H01L29/267 ,  H01L21/02524 ,  H01L21/02538 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1606 ,  H01L29/165

摘要： A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

摘要翻译： 半导体器件包括设置在衬底上的有源图案和与有源图案交叉的栅电极。 有源图案包括衬底上的第一缓冲器图案，第一缓冲器图案上的沟道图案，第一缓冲器图案和沟道图案之间的掺杂图案，以及掺杂图案和沟道图案之间的第二缓冲图案。 掺杂图案包括注入杂质的石墨烯。

公开(公告)号：US09318491B2

公开(公告)日：2016-04-19

申请号：US14547190

申请日：2014-11-19

申请人： Mirco Cantoro ,  Taeyong Kwon ,  Sangsu Kim ,  Jae-Hwan Lee

发明人： Mirco Cantoro ,  Taeyong Kwon ,  Sangsu Kim ,  Jae-Hwan Lee

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L27/092 ,  H01L27/088 ,  H01L29/36 ,  H01L29/16 ,  H01L29/20

CPC分类号： H01L27/0924 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/16 ,  H01L29/20 ,  H01L29/36

摘要： A semiconductor device includes a substrate, an insulating layer disposed on the substrate and having a trench exposing a surface portion of the substrate, and a channel-forming structure comprising crystalline semiconductor material. The channel-forming structure has a lower portion located in the trench and fins extending upright on the lower portion, where the fins are spaced from each other and are each narrower than an opening of the trench, and the lower portion of the channel forming structure has a higher crystal defect density than the fins of the channel forming structure.

摘要翻译： 半导体器件包括衬底，设置在衬底上并具有暴露衬底的表面部分的沟槽的绝缘层以及包含晶体半导体材料的沟道形成结构。 通道形成结构具有位于沟槽中的下部，并且在下部直立延伸的翅片，其中翅片彼此间隔开并且比沟槽的开口窄，并且通道形成结构的下部 具有比通道形成结构的翅片更高的晶体缺陷密度。

公开(公告)号：US08883651B2

公开(公告)日：2014-11-11

申请号：US13562826

申请日：2012-07-31

申请人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

发明人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306 ,  H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L21/762 ,  H01L29/165 ,  H01L21/324

CPC分类号： H01L29/165 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/76237 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7848

摘要： A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.

摘要翻译： 一种制造半导体器件的晶体管的方法，所述方法包括在半导体衬底上形成栅极图案，在栅极图案的侧壁上形成间隔物，湿蚀刻半导体衬底以在半导体衬底中形成第一凹部，其中 所述第一凹部邻近所述间隔件，并且湿蚀刻所述第一凹部以在所述半导体衬底中形成第二凹部。

公开(公告)号：US20110270077A1

公开(公告)日：2011-11-03

申请号：US12871232

申请日：2010-08-30

申请人： Jihoon Kang ,  Yong Choi ,  Wei Hu ,  Yoon Suk Huh ,  Key Jo Hong ,  Hyun Keong Lim ,  Sangsu Kim

发明人： Jihoon Kang ,  Yong Choi ,  Wei Hu ,  Yoon Suk Huh ,  Key Jo Hong ,  Hyun Keong Lim ,  Sangsu Kim

IPC分类号： A61B5/055

CPC分类号： G01T1/1603 ,  A61B5/055 ,  A61B6/5247 ,  G01T1/2985

摘要： Provided is a method for removing noise of a positron emission tomography (PET) signal in a PET-magnetic resonance imaging (MRI) fusion device without using an MRI radio frequency (RF) shield that degrades image quality. The method includes: (a1) converting a PET analog signal into a digital signal having a predetermined sampling frequency; (b1) determining whether the resulting PET digital signal is to be included in image reconstruction based on modeling using sampling points of the PET digital signal or an integration value of the PET digital signal; and (c1) extracting only the PET digital signal that will be included in image reconstruction. The method allows acquisition of molecular-level images without declined performance of a PET detector.

摘要翻译： 提供了一种在不使用降低图像质量的MRI射频（RF）屏蔽）的情况下去除PET-磁共振成像（MRI）融合装置中的正电子发射断层摄影（PET）信号的噪声的方法。 该方法包括：（a1）将PET模拟信号转换为具有预定采样频率的数字信号; （b1）基于使用PET数字信号的采样点或PET数字信号的积分值进行建模，确定所得到的PET数字信号是否包括在图像重建中; 和（c1）仅提取将包括在图像重建中的PET数字信号。 该方法允许采集分子水平图像而不降低PET检测器的性能。

公开(公告)号：US10411119B2

公开(公告)日：2019-09-10

申请号：US15093145

申请日：2016-04-07

申请人： Jae-Hwan Lee ,  Sangsu Kim ,  Sanghyuk Hong ,  Seung Mo Ha

发明人： Jae-Hwan Lee ,  Sangsu Kim ,  Sanghyuk Hong ,  Seung Mo Ha

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40 ,  H01L29/08

摘要： A method of fabricating a semiconductor device includes forming an active pattern protruding from a substrate, forming a liner layer on the active pattern, forming a sacrificial gate pattern on the liner layer and crossing the active pattern, forming source/drain regions on the active pattern and at both sides of the sacrificial gate pattern, forming an interlayer insulating layer to cover the source/drain regions, forming capping insulating patterns on the interlayer insulating layer to expose the sacrificial gate pattern, and removing the sacrificial gate pattern and the liner layer by an etching process using the capping insulating patterns as an etch mask to form a gap region exposing the active pattern. The active pattern includes a material having a lattice constant greater than a lattice constant of the substrate, and the capping insulating patterns include a material having an etch selectivity with respect to the liner layer.

公开(公告)号：US20110270076A1

公开(公告)日：2011-11-03

申请号：US12871220

申请日：2010-08-30

申请人： Jihoon Kang ,  Yong Choi ,  Key Jo Hong ,  Wei Hu ,  Hyun Keong Lim ,  Yoon Suk Huh ,  Sangsu Kim

发明人： Jihoon Kang ,  Yong Choi ,  Key Jo Hong ,  Wei Hu ,  Hyun Keong Lim ,  Yoon Suk Huh ,  Sangsu Kim

IPC分类号： A61B5/055

CPC分类号： A61B5/055 ,  A61B5/0035 ,  A61B6/5247 ,  G01R33/481 ,  G01T1/1603 ,  G01T1/2985

摘要： Provided is a method for removing noise of a positron emission tomography (PET) signal in a PET-magnetic resonance imaging (MRI) fusion device without using an MRI radio frequency (RF) shield that degrades image quality. The method includes: receiving a PET output signal from a PET-MRI fusion device and performing analog filtering by removing noise components due to an RF pulse frequency based on the relationship between the frequency of the PET output signal and a magnetic resonance (MR) RF frequency (Larmor frequency); and converting the filtered signal into a digital signal through sampling. The method allows acquisition of molecular-level images without declined performance of a PET detector in MRI environment.

摘要翻译： 提供了一种在不使用降低图像质量的MRI射频（RF）屏蔽）的情况下去除PET-磁共振成像（MRI）融合装置中的正电子发射断层摄影（PET）信号的噪声的方法。 该方法包括：从PET-MRI融合装置接收PET输出信号，并且通过基于PET输出信号的频率与磁共振（MR）RF之间的关系消除由于RF脉冲频率引起的噪声分量来执行模拟滤波 频率（拉莫尔频率）; 并通过采样将滤波后的信号转换成数字信号。 该方法允许采集分子水平的图像，而不会在MRI环境中PET检测器的性能下降。

公开(公告)号：US20150311341A1

公开(公告)日：2015-10-29

申请号：US14668490

申请日：2015-03-25

申请人： Sung Gi Hur ,  TaeYong Kwon ,  Sangsu Kim ,  Jungdal Choi

发明人： Sung Gi Hur ,  TaeYong Kwon ,  Sangsu Kim ,  Jungdal Choi

IPC分类号： H01L29/78 ,  H01L27/088

CPC分类号： H01L29/66553 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7849

摘要： A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.

摘要翻译： 半导体器件包括具有第一区域和第二区域的衬底，第一区域中包括第一鳍结构和第一栅电极的第一MOS晶体管，第一鳍结构具有第一缓冲图案，第二缓冲图案和 依次层叠在基板上的第一沟道图案和在第二区域中包括第二鳍结构和第二栅电极的第二MOS晶体管，第二鳍结构具有顺序堆叠的第三缓冲图案和第二沟道图案 在基板上。 还讨论了相关的制造方法。

公开(公告)号：US08880144B2

公开(公告)日：2014-11-04

申请号：US12904584

申请日：2010-10-14

申请人： Jihoon Kang ,  Yong Choi ,  Key Jo Hong ,  Wei Hu ,  Yoon Suk Huh ,  Hyun Keong Lim ,  Sangsu Kim

发明人： Jihoon Kang ,  Yong Choi ,  Key Jo Hong ,  Wei Hu ,  Yoon Suk Huh ,  Hyun Keong Lim ,  Sangsu Kim

IPC分类号： A61B5/05 ,  A61B6/03 ,  A61B6/00 ,  A61B5/055 ,  G01T1/29 ,  G01R33/48

CPC分类号： G01T1/2985 ,  A61B5/055 ,  A61B6/037 ,  A61B6/4258 ,  A61B6/508 ,  A61B6/5235 ,  G01R33/481 ,  G01T1/2935

摘要： Provided is a positron emission tomography (PET) detector module using Geiger-mode avalanche photodiode (GAPD) as a photosensor. The PET detector module includes: a PET detector unit with a scintillation crystal detecting gamma rays emitted from a living body and converting them into a scintillation light and a first GAPD photosensor and a second GAPD photosensor each being connected to either end of the scintillation crystal and converting the scintillation light into an electrical signal; and a depth of interaction (DOI) decoding unit receiving the signals from the PET detector unit and comparing amplitude of the signals detected by the first GAPD photosensor and the second GAPD photosensor, thereby providing the depth information where the gamma rays are incident on the scintillation crystal (DOI). The disclosed PET detector module can provide improved energy resolution and additional DOI information while maintaining linearity.

摘要翻译： 提供了使用盖革模式雪崩光电二极管（GAPD）作为光电传感器的正电子发射断层摄影（PET）检测器模块。 PET检测器模块包括：具有闪烁晶体的PET检测器单元，其检测从活体发射的γ射线并将其转换成闪烁光，并将第一GAPD光传感器和第二GAPD光电传感器连接到闪烁晶体的任一端，以及 将闪烁光转换成电信号; 以及相互作用深度（DOI）解码单元，其接收来自PET检测器单元的信号，并比较由第一GAPD光电传感器和第二GAPD光电传感器检测的信号的振幅，由此提供伽马射线入射在闪烁上的深度信息 晶体（DOI）。 所公开的PET检测器模块可以提供改进的能量分辨率和附加的DOI信息，同时保持线性。

公开(公告)号：US20160329414A1

公开(公告)日：2016-11-10

申请号：US15093145

申请日：2016-04-07

申请人： Jae-Hwan LEE ,  Sangsu Kim ,  Sanghyuk Hong ,  Seung Mo Ha

发明人： Jae-Hwan LEE ,  Sangsu Kim ,  Sanghyuk Hong ,  Seung Mo Ha

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40

CPC分类号： H01L29/66795 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7851

摘要： A method of fabricating a semiconductor device includes forming an active pattern protruding from a substrate, forming a liner layer on the active pattern, forming a sacrificial gate pattern on the liner layer and crossing the active pattern, forming source/drain regions on the active pattern and at both sides of the sacrificial gate pattern, forming an interlayer insulating layer to cover the source/drain regions, forming capping insulating patterns on the interlayer insulating layer to expose the sacrificial gate pattern, and removing the sacrificial gate pattern and the liner layer by an etching process using the capping insulating patterns as an etch mask to form a gap region exposing the active pattern. The active pattern includes a material having a lattice constant greater than a lattice constant of the substrate, and the capping insulating patterns include a material having an etch selectivity with respect to the liner layer.

摘要翻译： 制造半导体器件的方法包括形成从衬底突出的有源图案，在有源图案上形成衬垫层，在衬垫层上形成牺牲栅极图案并与有源图案交叉，在活性图案上形成源极/漏极区域 在牺牲栅极图案的两侧形成层间绝缘层以覆盖源极/漏极区域，在层间绝缘层上形成覆盖绝缘图案以暴露牺牲栅极图案，以及通过以下步骤去除牺牲栅极图案和衬底层： 使用封盖绝缘图案作为蚀刻掩模的蚀刻工艺来形成暴露活性图案的间隙区域。 活性图案包括晶格常数大于衬底的晶格常数的材料，并且封盖绝缘图案包括相对于衬垫层具有蚀刻选择性的材料。

公开(公告)号：US20130045589A1

公开(公告)日：2013-02-21

申请号：US13562826

申请日：2012-07-31

申请人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

发明人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

IPC分类号： H01L21/20 ,  H01L21/425

CPC分类号： H01L29/165 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/76237 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7848

摘要： A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.

摘要翻译： 一种制造半导体器件的晶体管的方法，所述方法包括在半导体衬底上形成栅极图案，在栅极图案的侧壁上形成间隔物，湿蚀刻半导体衬底以在半导体衬底中形成第一凹部，其中 所述第一凹部邻近所述间隔件，并且湿蚀刻所述第一凹部以在所述半导体衬底中形成第二凹部。