公开(公告)号：US10854523B2

公开(公告)日：2020-12-01

申请号：US16316108

申请日：2016-10-24

申请人： Mitsubishi Electric Corporation

发明人： Koichiro Nishizawa ,  Yoshitsugu Yamamoto ,  Katsumi Miyawaki ,  Shinsuke Watanabe ,  Toshihiko Shiga

IPC分类号： H01L23/02 ,  H01L23/04 ,  H01L21/48 ,  H01L23/10 ,  H01L23/34 ,  H01L23/552

摘要： A semiconductor device according to the present invention includes: a substrate; a heat generating portion provided on the substrate; a cap substrate provided above the substrate so that a hollow portion is provided between the substrate and the cap substrate; and a reflection film provided above the heat generating portion and reflecting a medium wavelength infrared ray. The reflection film reflects the infrared ray radiated to the cap substrate side through the hollow portion due to the temperature increase of the heat generating portion, so that the temperature increase of the cap substrate side can be suppressed. Because of this function, even if mold resin is provided on the cap substrate, increase of the temperature of the mold resin can be suppressed.

公开(公告)号：US20140353674A1

公开(公告)日：2014-12-04

申请号：US14174928

申请日：2014-02-07

申请人： Mitsubishi Electric Corporation

发明人： Hiroyuki Kinoshita ,  Yoshitsugu Yamamoto ,  Tetsuo Kunii

IPC分类号： H01L29/20 ,  H01L29/778

CPC分类号： H01L29/2003 ,  H01L29/66462 ,  H01L29/772 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7787

摘要： A semiconductor device includes a substrate, a buffer layer of GaN containing at least one of Fe and C and disposed on the substrate, a channel layer of GaN disposed on the buffer layer and through which electrons travel, an electron supply layer disposed on the channel layer and producing a two-dimensional electron gas in the channel layer, a gate electrode, a drain electrode, and a source electrode. Recovery time of a drain current of the semiconductor device is no more than 5 seconds, where the recovery time is defined as the period of time after the semiconductor device is stopped from outputting high frequency power until the change in the drain current, after the stopping of the semiconductor device, reaches 95% of the change in the drain current occurring during the first 10 seconds after the stopping of the semiconductor device.

摘要翻译： 半导体器件包括衬底，包含Fe和C中的至少一个并且设置在衬底上的GaN的缓冲层，设置在缓冲层上并通过电子行进的GaN的沟道层，设置在沟道上的电子供给层 并且在沟道层中产生二维电子气，栅电极，漏电极和源电极。 半导体器件的漏极电流的恢复时间不超过5秒，其中恢复时间被定义为半导体器件停止之后的时间段，以在停止之后输出高频功率直到漏极电流的变化 达到半导体器件停止后的前10秒内发生的漏极电流变化的95％。

公开(公告)号：US09508564B2

公开(公告)日：2016-11-29

申请号：US14425142

申请日：2013-07-19

申请人： Mitsubishi Electric Corporation

发明人： Yoshinori Yokoyama ,  Kazuyo Endo ,  Jun Fujita ,  Shinnosuke Soda ,  Kazuyasu Nishikawa ,  Yoichi Nogami ,  Yoshitsugu Yamamoto ,  Akira Inoue

IPC分类号： H01L21/00 ,  H01L21/52 ,  H01L23/10 ,  H01L21/50 ,  H01L21/56 ,  H01L21/78

CPC分类号： H01L21/52 ,  H01L21/50 ,  H01L21/561 ,  H01L21/78 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of semiconductor element is formed on a substrate. A plurality of sealing windows and a support portion supporting the plurality of sealing windows are formed on a SOI substrate. The SOI substrate is pressured against the substrate by using a pressurizing member and the plurality of sealing windows of the SOI substrate is bonded to the substrate via a low melting point glass member arranged around the plurality of semiconductor elements. The support portion is separated from the plurality of sealing windows bonded to the substrate.

摘要翻译： 在基板上形成多个半导体元件。 在SOI衬底上形成有多个密封窗和支撑多个密封窗的支撑部。 通过使用加压构件将SOI衬底压靠在衬底上，并且SOI衬底的多个密封窗口通过布置在多个半导体元件周围的低熔点玻璃构件接合到衬底。 支撑部分与结合到基底的多个密封窗口分离。

公开(公告)号：US20140134835A1

公开(公告)日：2014-05-15

申请号：US13953857

申请日：2013-07-30

申请人： Mitsubishi Electric Corporation

发明人： Kenichiro Kurahashi ,  Yoshitaka Kamo ,  Yoshitsugu Yamamoto

IPC分类号： H01L21/28

CPC分类号： H01L21/28017 ,  H01L21/0272 ,  H01L21/0331 ,  H01L21/28581 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/778

摘要： A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.

摘要翻译： 一种制造半导体器件的方法包括在半导体层上形成第一层，在第一层上形成第二层，在第二层上形成图案化掩模，蚀刻并除去第二层未覆盖的第二层的一部分 在图案化掩模之后，在湿蚀刻之后，在第一层上湿蚀刻到小于图案化掩模的宽度的宽度，在半导体层上形成绝缘层，去除第一层和第二层，以在第 绝缘层，并且在通过所述开口暴露的所述半导体层的表面上形成栅电极。

公开(公告)号：US20150243530A1

公开(公告)日：2015-08-27

申请号：US14425142

申请日：2013-07-19

申请人： Mitsubishi Electric Corporation

发明人： Yoshinori Yokoyama ,  Kazuyo Endo ,  Jun Fujita ,  Shinnosuke Soda ,  Kazuyasu Nishikawa ,  Yoichi Nogami ,  Yoshitsugu Yamamoto ,  Akira Inoue

IPC分类号： H01L21/52 ,  H01L21/78

CPC分类号： H01L21/52 ,  H01L21/50 ,  H01L21/561 ,  H01L21/78 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of semiconductor element is formed on a substrate. A plurality of sealing windows and a support portion supporting the plurality of sealing windows are formed on a SOI substrate. The SOI substrate is pressured against the substrate by using a pressurizing member and the plurality of sealing windows of the SOI substrate is bonded to the substrate via a low melting point glass member arranged around the plurality of semiconductor elements. The support portion is separated from the plurality of sealing windows bonded to the substrate.

摘要翻译： 在基板上形成多个半导体元件。 在SOI衬底上形成有多个密封窗和支撑多个密封窗的支撑部。 通过使用加压构件将SOI衬底压靠在衬底上，并且SOI衬底的多个密封窗口通过布置在多个半导体元件周围的低熔点玻璃构件接合到衬底。 支撑部分与结合到基底的多个密封窗口分离。

公开(公告)号：US08816493B2

公开(公告)日：2014-08-26

申请号：US13921695

申请日：2013-06-19

申请人： Mitsubishi Electric Corporation

发明人： Yoichi Nogami ,  Yoshitsugu Yamamoto ,  Akira Inoue ,  Yoshinori Yokoyama ,  Jun Fujita ,  Kazuyo Endo ,  Shinnosuke Soda ,  Kazuyasu Nishikawa

IPC分类号： H01L23/12 ,  H01L29/78 ,  H01L23/00 ,  H01L23/60

CPC分类号： H01L23/564 ,  H01L23/04 ,  H01L23/06 ,  H01L23/10 ,  H01L23/60 ,  H01L23/66 ,  H01L29/78 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a substrate; a semiconductor element on the substrate; an interconnection on the substrate and electrically connected to the semiconductor element; a window frame member on the substrate, surrounding the semiconductor element, and in contact with the interconnection; and a sealing window bonded to the window frame member and encapsulating the semiconductor element. The window frame member is a low melting glass and has a sheet resistance of 106-1010 Ω/□.

摘要翻译： 半导体器件包括：衬底; 衬底上的半导体元件; 在所述基板上的与所述半导体元件电连接的互连; 在所述基板上的窗框构件，围绕所述半导体元件并与所述互连件接触; 以及密封窗，其结合到所述窗框构件并封装所述半导体元件。 窗框构件是低熔点玻璃，并且具有106-1010＆OHgr / /□的薄层电阻。

公开(公告)号：US20140077280A1

公开(公告)日：2014-03-20

申请号：US13921695

申请日：2013-06-19

申请人： Mitsubishi Electric Corporation

发明人： Yoichi Nogami ,  Yoshitsugu Yamamoto ,  Akira Inoue ,  Yoshinori Yokoyama ,  Jun Fujita ,  Kazuyo Endo ,  Shinnosuke Soda ,  Kazuyasu Nishikawa

IPC分类号： H01L23/00 ,  H01L23/60 ,  H01L29/78

CPC分类号： H01L23/564 ,  H01L23/04 ,  H01L23/06 ,  H01L23/10 ,  H01L23/60 ,  H01L23/66 ,  H01L29/78 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a substrate; a semiconductor element on the substrate; an interconnection on the substrate and electrically connected to the semiconductor element; a window frame member on the substrate, surrounding the semiconductor element, and in contact with the interconnection; and a sealing window bonded to the window frame member and encapsulating the semiconductor element. The window frame member is a low melting glass and has a sheet resistance of 106-1010 Ω/□.

摘要翻译： 半导体器件包括：衬底; 衬底上的半导体元件; 在所述基板上的与所述半导体元件电连接的互连; 在所述基板上的窗框构件，围绕所述半导体元件并与所述互连件接触; 以及密封窗，其结合到所述窗框构件并封装所述半导体元件。 窗框构件是低熔点玻璃，并且具有106-1010＆OHgr / /□的薄层电阻。

公开(公告)号：US09159654B2

公开(公告)日：2015-10-13

申请号：US14504463

申请日：2014-10-02

申请人： Mitsubishi Electric Corporation

发明人： Youichi Nogami ,  Hidetoshi Koyama ,  Yoshitsugu Yamamoto

IPC分类号： H01L23/48 ,  H01L23/485 ,  H01L23/482

CPC分类号： H01L23/4855 ,  H01L23/481 ,  H01L23/482 ,  H01L23/4821 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having opposed main and back surfaces; first and second electrodes in a device region of the substrate, and spaced apart from each other; a metal film on the main surface and joined to the second electrode; an air gap between part of the main surface and the metal film, enveloping the first electrode, and having an opening; a cured resin closing the opening; a liquid repellent film increasing contact angle of the resin, relative to contact angles on the substrate and the metal film; a first metal film joined to the metal film, covering the metal film and the cured resin, and joined to an outer peripheral region of the substrate, at a periphery of the device region; and a second metal film on the back surface and connected to the first electrode through a via hole penetrating the substrate.

摘要翻译： 半导体器件包括具有相对的主表面和后表面的半导体衬底; 第一和第二电极在衬底的器件区域中并且彼此间隔开; 主表面上的金属膜并与第二电极接合; 主表面的一部分和金属膜之间的气隙，包围第一电极，并具有开口; 封闭开口的固化树脂; 相对于基板和金属膜上的接触角，增加树脂的接触角的防液膜; 与金属膜接合的第一金属膜，覆盖金属膜和固化树脂，并在该器件区域的周围与基板的外周区域接合; 以及在后表面上的第二金属膜，并通过穿透基板的通孔连接到第一电极。

公开(公告)号：US09117742B2

公开(公告)日：2015-08-25

申请号：US14174928

申请日：2014-02-07

申请人： Mitsubishi Electric Corporation

发明人： Hiroyuki Kinoshita ,  Yoshitsugu Yamamoto ,  Tetsuo Kunii

IPC分类号： H01L31/0328 ,  H01L29/20 ,  H01L29/778 ,  H01L29/772 ,  H01L29/66

CPC分类号： H01L29/2003 ,  H01L29/66462 ,  H01L29/772 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7787

摘要： A semiconductor device includes a substrate, a buffer layer of GaN containing at least one of Fe and C and disposed on the substrate, a channel layer of GaN disposed on the buffer layer and through which electrons travel, an electron supply layer disposed on the channel layer and producing a two-dimensional electron gas in the channel layer, a gate electrode, a drain electrode, and a source electrode. Recovery time of a drain current of the semiconductor device is no more than 5 seconds, where the recovery time is defined as the period of time after the semiconductor device is stopped from outputting high frequency power until the change in the drain current, after the stopping of the semiconductor device, reaches 95% of the change in the drain current occurring during the first 10 seconds after the stopping of the semiconductor device.

摘要翻译： 半导体器件包括衬底，包含Fe和C中的至少一个并且设置在衬底上的GaN的缓冲层，设置在缓冲层上并通过电子行进的GaN的沟道层，设置在沟道上的电子供给层 并且在沟道层中产生二维电子气，栅电极，漏电极和源电极。 半导体器件的漏极电流的恢复时间不超过5秒，其中恢复时间被定义为半导体器件停止之后的时间段，以在停止之后输出高频功率直到漏极电流的变化 达到半导体器件停止后的前10秒内发生的漏极电流变化的95％。

公开(公告)号：US20150054137A1

公开(公告)日：2015-02-26

申请号：US14504463

申请日：2014-10-02

申请人： Mitsubishi Electric Corporation

发明人： Youichi Nogami ,  Hidetoshi Koyama ,  Yoshitsugu Yamamoto

IPC分类号： H01L23/485 ,  H01L23/48 ,  H01L23/482

CPC分类号： H01L23/4855 ,  H01L23/481 ,  H01L23/482 ,  H01L23/4821 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having opposed main and back surfaces; first and second electrodes in a device region of the substrate, and spaced apart from each other; a metal film on the main surface and joined to the second electrode; an air gap between part of the main surface and the metal film, enveloping the first electrode, and having an opening; a cured resin closing the opening; a liquid repellent film increasing contact angle of the resin, relative to contact angles on the substrate and the metal film; a first metal film joined to the metal film, covering the metal film and the cured resin, and joined to an outer peripheral region of the substrate, at a periphery of the device region; and a second metal film on the back surface and connected to the first electrode through a via hole penetrating the substrate.

摘要翻译： 半导体器件包括具有相对的主表面和后表面的半导体衬底; 第一和第二电极在衬底的器件区域中并且彼此间隔开; 主表面上的金属膜并与第二电极接合; 主表面的一部分和金属膜之间的气隙，包围第一电极，并具有开口; 封闭开口的固化树脂; 相对于基板和金属膜上的接触角，增加树脂的接触角的防液膜; 与金属膜接合的第一金属膜，覆盖金属膜和固化树脂，并在该器件区域的周围与基板的外周区域接合; 以及在后表面上的第二金属膜，并通过穿透基板的通孔连接到第一电极。