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    High density integrated circuit pad structures
    3.
    发明授权
    High density integrated circuit pad structures 失效
    高密度集成电路板结构

    公开(公告)号：US5834849A

    公开(公告)日：1998-11-10

    申请号：US600339

    申请日：1996-02-13

    申请人： Christopher F. Lane

    发明人： Christopher F. Lane

    IPC分类号： H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/4855 ,  H01L2924/0002

    摘要： An integrated circuit with high density pad structures is provided. The circuit has circuitry covered by an insulating layer. Pads are formed on the insulating layer overlapping the circuitry. A pattern of holes in the insulating layer allows electrical connections to be formed between the pads and the underlying circuitry. Because the pads are formed on top of the circuitry, the die area occupied by pads is reduced relative to the die area occupied by circuitry. The pads are suitable for flip-chip bonding to a package such as a multichip module or conventional wire bonding.

    摘要翻译： 提供了一种具有高密度焊盘结构的集成电路。 该电路具有由绝缘层覆盖的电路。 在与电路重叠的绝缘层上形成垫。 绝缘层中的孔的图案允许在焊盘和下面的电路之间形成电连接。 由于焊盘形成在电路的顶部，所以由焊盘占据的管芯面积相对于由电路占据的管芯面积减小。 这些焊盘适用于与诸如多芯片模块或常规引线接合的封装的倒装芯片接合。

    Hybrid process for SBD metallurgies
    4.
    发明授权
    Hybrid process for SBD metallurgies 失效
    SBD冶金的混合工艺

    公开(公告)号：US4272561A

    公开(公告)日：1981-06-09

    申请号：US43416

    申请日：1979-05-29

    申请人： Laura B. Rothman ,  Paul A. Totta ,  James F. White

    发明人： Laura B. Rothman ,  Paul A. Totta ,  James F. White

    IPC分类号： H01L21/306 ,  H01L21/027 ,  H01L21/28 ,  H01L21/285 ,  H01L21/338 ,  H01L23/485 ,  H01L21/283 ,  H01L29/48

    CPC分类号： H01L29/66848 ,  H01L21/0272 ,  H01L21/28 ,  H01L21/28512 ,  H01L23/4855 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S438/951

    摘要： A method for forming thin film patterns in the fabrication of integrated circuits utilizing a lift-off mask in an inverse vertical relationship with the desired metal film. The method involves the preliminary blanket deposition of the metal in-point, followed by a coating of a patterned lift-off mask over which is blanket coated a dry-etch resistant material with subsequent removal of the lift-off mask, and dry etching of the exposed metal film. In one embodiment the dry-etch mask can comprise a diverse metal layer when a dry-etch ambient is employed which is passive to the diverse metal. In another embodiment, where dry etch ambients are employed which are corrosive to the diverse metal which is desired in the final structure, it can be covered with a blanket layer of any convenient dry-etch resistant material, such as magnesium oxide, prior to removal of the lift-off mask. This method has effective application in the fabrication of Schottky barrier diodes, transistors, and other electronic components or discrete and integrated devices requiring high quality metal to semiconductor junctions or interfaces.

    摘要翻译： 在利用与期望的金属膜成反向垂直关系的剥离掩模的集成电路的制造中形成薄膜图案的方法。 该方法包括金属入点的初步覆盖沉积，随后涂覆图案化剥离掩模，在其上涂覆耐干腐蚀材料，随后除去剥离掩模，并干法蚀刻 暴露的金属膜。 在一个实施例中，当使用干蚀刻环境时，干蚀刻掩模可以包括不同的金属层，其对于多种金属是被动的。 在另一个实施方案中，当采用对最终结构中所需的多种金属具有腐蚀性的干蚀刻环境时，其可以在除去之前用诸如氧化镁的任何方便的耐干蚀刻材料的覆盖层覆盖 的剥离面具。 该方法在制造肖特基势垒二极管，晶体管和其它电子元件或需要高质量金属至半导体结或接口的离散和集成器件方面具有有效的应用。

    Method of forming electrodes on the surface of a semiconductor substrate
    8.
    发明授权
    Method of forming electrodes on the surface of a semiconductor substrate 失效
    在半导体衬底的表面上形成电极的方法

    公开(公告)号：US4337115A

    公开(公告)日：1982-06-29

    申请号：US137813

    申请日：1980-04-04

    申请人： Masashi Ikeda ,  Shintaro Ito

    发明人： Masashi Ikeda ,  Shintaro Ito

    IPC分类号： H01L21/306 ,  H01L21/027 ,  H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  B05D5/12 ,  C23F1/02

    CPC分类号： H01L21/7688 ,  H01L21/0272 ,  H01L23/4855 ,  H01L2924/0002 ,  Y10S438/944 ,  Y10S438/951

    摘要： There is provided a method of forming an electrode on the surface of a semiconductor substrate which comprises the steps of(A) depositing on the surface of a semiconductor substrate an insulation layer provided with at least one opening for contact between the electrode and the semiconductor substrate;(B) coating a plurality of spacer layers made of insulation material on the surface of the insulation layer inclusive of the contact opening;(C) selectively depositing a photoresist layer on the uppermost are of said plural spacer layers, said uppermost spacer layer in direct contact with the photoresist layer being designed to be etched at a lower rate than the immediately underlying spacer layer;(D) using the photoresist layers as a mask to selectively etch the spacer layers until said opening is exposed;(E) depositing a metal layer on the surface of the semiconductor substrate inclusive of said opening and photoresist layer; and(F) removing the photoresist layer and the portions of the metal layer formed, such that the portion of the metal layer which is deposited on the surface of the semiconductor substrate exposed through the opening constitute the electrode, and the spacer layers remaining on the insulation layer form protective layers for the surface of the semiconductor substrate.

    摘要翻译： 提供了一种在半导体衬底的表面上形成电极的方法，其包括以下步骤：（A）在半导体衬底的表面上沉积设置有至少一个用于接触电极和半导体衬底之间的开口的绝缘层 ; （B）在绝缘层的包括接触开口的表面上涂覆由绝缘材料制成的多个隔离层; （C）在所述多个间隔层的最上面选择性地沉积光致抗蚀剂层，与光致抗蚀剂层直接接触的所述最上层间隔层被设计为以比最接近的间隔层更低的速率进行蚀刻; （D）使用光致抗蚀剂层作为掩模来选择性地蚀刻间隔层，直到所述开口暴露; （E）在包括所述开口和光致抗蚀剂层的半导体衬底的表面上沉积金属层; 和（F）去除光致抗蚀剂层和形成的金属层的部分，使得沉积在通过开口暴露的半导体衬底的表面上的金属层的部分构成电极，并且间隔层保留在 绝缘层形成用于半导体衬底的表面的保护层。

    Etched silicon washed emitter process
    9.
    发明授权
    Etched silicon washed emitter process 失效
    蚀刻有机硅清洗发酵工艺

    公开(公告)号：US3926695A

    公开(公告)日：1975-12-16

    申请号：US53704574

    申请日：1974-12-27

    申请人： ITT

    发明人： U AUNG SAN

    IPC分类号： H01L21/00 ,  H01L23/485 ,  H01L21/223

    CPC分类号： H01L23/4855 ,  H01L21/00 ,  H01L2924/0002 ,  H01L2924/00

    摘要： This relates to a shallow diffused washed emitter process. Prior to diffusion of an emitter into the base region of an active element, a portion of the surface base region is etched away. During this process, lateral etch occurs and extends beneath a portion of the oxide mask. During subsequent diffusion of the emitter, greater lateral diffusion occurs immediately beneath the oxide layer. Deposition of a metal contact causes a closed loop cavity around the periphery of the emitter area to be formed. In this way, the metal contacts only the broadest portion of the emitter region.