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公开(公告)号：US07290271B2
公开(公告)日：2007-10-30
申请号：US11175022
申请日：2005-07-06
IPC分类号： G11B33/14
CPC分类号： G11B17/05
摘要： An optical disk apparatus according to the invention comprises a housing, a tray retractably mounted in the housing, and a bezel 10 adapted to close an opening of the housing 2 when the tray is accommodated in the housing 2. An electrically conductive metallic member 15 is disposed in at least one of main flat portions in the bezel 10. When the tray is accommodated in the housing, at least one surface of the conductive metallic member 15 is in contact with the housing.
摘要翻译： 根据本发明的光盘装置包括壳体，可缩回地安装在壳体中的托盘和适于当托盘容纳在壳体2中时关闭壳体2的开口的边框10。 导电金属构件15设置在边框10的至少一个主平面部分中。 当托盘容纳在壳体中时，导电金属构件15的至少一个表面与壳体接触。
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公开(公告)号：US06535993B1
公开(公告)日：2003-03-18
申请号：US09464768
申请日：1999-12-16
申请人： Mitsuhiro Hamada , Jun Ohtani
发明人： Mitsuhiro Hamada , Jun Ohtani
IPC分类号： G06F1118
CPC分类号： G11C29/56 , G11C2029/5606
摘要： Row faulty bit storage memory corresponding to a spare row circuit and a column faulty bit storage memory corresponding to a spare column circuit are provided independently of each other, and faulty bits of these faulty bit storage memories are counted by a row faulty bit counter and a column faulty bit counter, respectively. Repairability of the faulty row and repairability of the faulty column are determined using the row faulty bit storage memory and the column faulty bit storage memory. A time required for determining repairability of the faulty bit of a semiconductor memory is reduced, and a storage capacity of the faulty bit storage memory is reduced.
摘要翻译： 彼此独立地提供与备用行电路对应的行故障位存储存储器和对应于备用列电路的列故障位存储存储器，并且这些故障位存储存储器的故障位由行错位位计数器和 列故障位计数器。 故障列的可修复性和故障列的可修复性使用行故障位存储存储器和列故障位存储存储器来确定。 确定半导体存储器的故障位的可修复性所需的时间被减少，并且故障位存储存储器的存储容量减小。
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公开(公告)号：US5267205A
公开(公告)日：1993-11-30
申请号：US633845
申请日：1990-12-26
申请人： Mitsuhiro Hamada
发明人： Mitsuhiro Hamada
IPC分类号： G11C7/06 , G11C11/401 , G11C11/413 , G11C29/00 , G11C29/04 , G11C7/00 , G11C11/40
CPC分类号： G11C29/835 , G11C7/062
摘要： A semiconductor memory device with a redundant configuration according to the present invention includes a roll call circuit which turns an output signal of a sense amplifier compulsorily to a signal of a predetermined logical level when a portion constituting the redundant configuration is accessed, and turns an output signal of the output control circuit to that of the same predetermined logical level when a write instruction is given outside a normal level. Whether a spare memory cell is accessed can be checked in every output and the redundant configuration can operate with stability.
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公开(公告)号：US08354712B2
公开(公告)日：2013-01-15
申请号：US13023889
申请日：2011-02-09
申请人： Mitsuhiro Hamada , Katsuyoshi Jokyu
发明人： Mitsuhiro Hamada , Katsuyoshi Jokyu
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L29/7827 , H01L21/266 , H01L29/66666
摘要： A body contact layer 18 is formed on the side of a recessed structure 17 as well as in the bottom of the recessed structure 17, so that a contact area between the body contact layer 18 and a well layer 12 is increased and the amount of dopant implanted to the body contact layer 18 is suppressed.
摘要翻译： 身体接触层18形成在凹陷结构17的侧面以及凹陷结构17的底部，使得身体接触层18和阱层12之间的接触面积增加，并且掺杂剂的量 植入身体接触层18被抑制。
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5.发明授权Semiconductor memory device enabling test of timing standard for strobe signal and data signal with ease, and subsidiary device and testing device thereof 失效半导体存储器件能够轻松地测试选通信号和数据信号的定时标准，以及其辅助设备和测试装置公开(公告)号：US06339555B1
公开(公告)日：2002-01-15
申请号：US09759358
申请日：2001-01-16
申请人： Mitsuhiro Hamada , Kenichi Yasuda
发明人： Mitsuhiro Hamada , Kenichi Yasuda
IPC分类号： G11C700
CPC分类号： G11C7/1066 , G11C29/48
摘要： A first delay circuit for delaying a data signal IND output from a memory circuit and a second delay circuit for delaying a strobe signal INS, and a latch circuit for latching data according to the outputs of the first and the second delay circuits are provided as a test circuit inside a DDR SDRAM. A tester can observe results of latching by the latch circuit to facilitate determination whether the data signal and the strobe signal have a correlation adapted to a standard. Accordingly, such a DDR SDRAM can be provided that is capable of conducting an examination whether the device meets a tDQSQ standard defining a correlation between the strobe signal DQS and the data signal DQ with ease.
摘要翻译： 用于延迟从存储器电路输出的数据信号IND和用于延迟选通信号INS的第二延迟电路的第一延迟电路和用于根据第一和第二延迟电路的输出来锁存数据的锁存电路被提供为 DDR SDRAM内部的测试电路。 测试者可以观察到锁存电路锁存的结果，以便于确定数据信号和选通信号是否具有适应标准的相关性。 因此，可以提供这样的DDR SDRAM，其能够进行检查，无论设备是否满足定义选通信号DQS和数据信号DQ之间的相关性的tDQSQ标准。
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6.发明授权Semiconductor device capable of reducing cost of analysis for finding replacement address in memory array 失效能够降低分析成本的半导体器件，用于在存储器阵列中寻找替换地址公开(公告)号：US06297997B1
公开(公告)日：2001-10-02
申请号：US09459538
申请日：1999-12-13
申请人： Jun Ohtani , Mitsuhiro Hamada
发明人： Jun Ohtani , Mitsuhiro Hamada
IPC分类号： G11C700
CPC分类号： G11C29/44 , G11C2029/1208
摘要： In a semiconductor device including banks A and B, testing and redundancy analysis of the bank B are first carried out by using a conventional tester, and redundancy replacement is carried out. Then, the bank A is tested by a BIST circuit and the test result of each bit is written to the bank B. By using the bank B as a memory for defect analysis, a tester connected to the semiconductor device while testing the bank A does not need a large capacity analysis memory. Thus, an inexpensive redundancy analysis system can be provided.
摘要翻译： 在包括银行A和B的半导体装置中，首先通过使用常规的测试器进行银行B的测试和冗余分析，并进行冗余替换。 然后，银行A由BIST电路测试，每个位的测试结果写入银行B.通过使用库B作为缺陷分析的存储器，在测试银行A时连接到半导体器件的测试器 不需要大容量分析内存。 因此，可以提供廉价的冗余分析系统。
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公开(公告)号：US20110233663A1
公开(公告)日：2011-09-29
申请号：US13023889
申请日：2011-02-09
申请人： Mitsuhiro Hamada , Katsuyoshi Jokyu
发明人： Mitsuhiro Hamada , Katsuyoshi Jokyu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/266 , H01L29/66666
摘要： A body contact layer 18 is formed on the side of a recessed structure 17 as well as in the bottom of the recessed structure 17, so that a contact area between the body contact layer 18 and a well layer 12 is increased and the amount of dopant implanted to the body contact layer 18 is suppressed.
摘要翻译： 身体接触层18形成在凹陷结构17的侧面以及凹陷结构17的底部，使得身体接触层18和阱层12之间的接触面积增加，并且掺杂剂的量 植入身体接触层18被抑制。
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公开(公告)号：US07968942B2
公开(公告)日：2011-06-28
申请号：US12260562
申请日：2008-10-29
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L29/7813
摘要： The present invention provides a semiconductor apparatus having high reliability with respect to a withstand voltage, leakage characteristics, etc. by disposing a structure of preventing stress occurring by metal wiring from directly acting on a trench relating to the semiconductor apparatus having a trench gate. The semiconductor apparatus of the invention includes a semiconductor substrate including a semiconductor layer having a predetermined impurity concentration, a trench gate formed in the semiconductor layer by filling a stripe-shaped trench by a conductor layer on which surface and interface a gate oxide film is formed, an insulating film covering a surface of the semiconductor layer and having a source contact opening, a source region formed in the semiconductor layer, a source electrode formed on the surface of the semiconductor layer so as to electrically connect to the source region through the source contact opening, a gate peripheral wiring connected to the trench gate at a peripheral edge part of the trench gate, a gate electrode separately formed from the source electrode, formed above the surface of the semiconductor layer and connected to the gate peripheral wiring and a drain electrode formed on an surface of the semiconductor substrate opposite to the surface of the semiconductor layer, wherein the trench gate is formed so as to avoid a corner portion of the source contact opening of the source electrode.
摘要翻译： 本发明通过设置防止金属布线发生的应力直接作用在具有沟槽栅的半导体装置的沟槽上的结构，提供了一种相对于耐电压，漏电特性等具有高可靠性的半导体装置。 本发明的半导体装置包括：半导体衬底，其包括具有预定杂质浓度的半导体层;沟槽栅极，通过在其上形成栅极氧化膜的表面和界面的导体层填充条形沟槽而形成在半导体层中 覆盖半导体层的表面并具有源极接触开口的绝缘膜，形成在半导体层中的源极区域，形成在半导体层的表面上的源极，以便通过源极电连接到源极区域 接触开口，在沟槽栅极的外围边缘部分处连接到沟槽栅极的栅极周边布线，形成在源电极上的栅电极，形成在半导体层的表面上并连接到栅极外围布线和漏极 形成在半导体衬底的与半导体表面相对的表面上的电极 导电层，其中形成沟槽栅极以避免源电极的源极接触开口的角部。
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公开(公告)号：US20080084093A1
公开(公告)日：2008-04-10
申请号：US11905466
申请日：2007-10-01
摘要： A pair of left and right rockers are arranged along a vehicle longitudinal direction at lower portions of two vehicle lateral direction ends of a body. A floor cross-member is provided at each of two vehicle lateral direction end portions of a cross member, which is arranged along the vehicle lateral direction at a lower portion of the body. A lower side joining flange of each rocker and a vehicle lateral direction outer side end portion of a bottom wall portion of each floor cross-member are joined together by a mount bracket. With the rocker and/or the floor cross-member, the mount bracket forms a closed cavity, of which a vehicle lateral direction outer side portion extends beneath a rocker inner. A nut is provided in the closed cavity for joining the body with a body mount, which is fixed to a chassis frame.
摘要翻译： 一对左右摇摆器沿着车身纵向在身体的两个车辆横向端的下部布置。 在横向构件的两个车辆横向端部的每一个处设置有地板横梁，该横向构件沿着车身横向方向布置在主体的下部。 每个摇臂的下侧接合凸缘和每个地板横梁的底壁部分的车辆横向外侧端部通过安装支架连接在一起。 通过摇杆和/或地板横梁，安装支架形成一个封闭的空腔，其车辆横向外侧部分在摇臂内部延伸。 螺母设置在封闭空腔中，用于将主体与固定在底架上的主体安装座相连接。
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10.发明授权Semiconductor inspecting system for inspecting a semiconductor integrated circuit device, and semiconductor inspecting method using the same 失效用于检查半导体集成电路器件的半导体检查系统以及使用其的半导体检查方法公开(公告)号：US06750672B2
公开(公告)日：2004-06-15
申请号：US10119067
申请日：2002-04-10
IPC分类号： G01R3102
CPC分类号： G01R31/2882
摘要： An apparatus to be inspected is mounted on one surface of a socket board. An auxiliary inspecting apparatus for adjusting timing of write signals transmitted from a semiconductor inspecting apparatus is mounted on the other surface of the socket board. Input/output (I/O) pins of the auxiliary inspecting apparatus are connected to corresponding I/O pins of the inspected device via through holes in the socket board on a one-to-one basis. This semiconductor inspecting method is thus capable of easily suppressing the delay difference between a plurality of signals output from the semiconductor inspecting apparatus.
摘要翻译： 被检查的装置安装在插座板的一个表面上。 用于调整从半导体检查装置发送的写入信号的定时的辅助检查装置安装在插座板的另一个表面上。 辅助检测装置的输入/输出（I / O）引脚通过一个一对一的插孔板上的通孔连接到被检查设备的相应I / O引脚。 因此，该半导体检查方法能够容易地抑制从半导体检查装置输出的多个信号之间的延迟差。
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