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32 条记录 (耗时 0.02 秒)

    Crystal oscillator circuit
    1.
    发明授权
    Crystal oscillator circuit 失效
    晶振电路

    公开(公告)号：US5545941A

    公开(公告)日：1996-08-13

    申请号：US489714

    申请日：1995-06-13

    申请人： Mitsuo Soneda ,  Takahiro Seki

    发明人： Mitsuo Soneda ,  Takahiro Seki

    IPC分类号： H03B5/32 ,  H03B5/36 ,  H03K3/013 ,  H03K3/354

    CPC分类号： H03K3/3545 ,  H03K3/013

    摘要： A crystal oscillator circuit including a quartz vibrator; an inverter circuit connected in parallel to the quartz vibrator and comprised of at least two transistors connected at their output ends to a first power-supply potential or a second power-supply potential lower than the first power-supply potential; a first current mirror circuit, with one current input-output end connected to a connection line with the inverter circuit of the first power-supply potential, the other current input-output end connected to the output end of the oscillator circuit; and either a second current mirror circuit having two current input-output ends, one current input-output end connected to a connection line with the inverter circuit of the second power-supply potential, the other current input-output end connected to the output end of the oscillator circuit, current flowing to one current input-output end, current flowing to the other current input-output end, and the level of the output end of the oscillator circuit being shifted to the level of the second power-supply potential when the output end of the inverter circuit is connected to the second power-supply potential or a circuit for shifting the level of the output end of the inverter circuit to the level of a second power-supply potential in accordance with the level of the input end of the inverter circuit when the output end of the circuit is connected to a second power-supply potential.

    摘要翻译： 一种包括石英振子的晶体振荡器电路; 与石英振子并联连接的逆变器电路，由至少两个在其输出端连接到第一电源电位或低于第一电源电位的第二电源电位的晶体管; 第一电流镜电路，其一个电流输入输出端连接到与第一电源电位的反相器电路的连接线，另一个电流输入 - 输出端连接到振荡器电路的输出端; 以及具有两个电流输入 - 输出端的第二电流镜电路，一个电流输入 - 输出端连接到与第二电源电位的反相器电路的连接线，另一个电流输入 - 输出端连接到输出端 的振荡器电路，流向一个电流输入 - 输出端的电流，流向另一个电流输入 - 输出端的电流，以及振荡器电路的输出端的电平被移动到第二电源电位的电平，当 逆变器电路的输出端连接到第二电源电位或用于根据输入端的电平将逆变器电路的输出端的电平转换到第二电源电位的电平的电路 的电路的输出端连接到第二电源电位。

    Semiconductor device replica circuit for monitoring critical path and construction method of the same
    2.
    发明授权
    Semiconductor device replica circuit for monitoring critical path and construction method of the same 有权
    用于监测关键路径的半导体器件复制电路及其施工方法

    公开(公告)号：US06414527B1

    公开(公告)日：2002-07-02

    申请号：US09484240

    申请日：2000-01-18

    申请人： Katsunori Seno ,  Takahiro Seki ,  Tetsuo Kondo

    发明人： Katsunori Seno ,  Takahiro Seki ,  Tetsuo Kondo

    IPC分类号： H03L706

    CPC分类号： G06F1/3296 ,  G06F1/10 ,  G06F1/3203 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  Y02D10/172

    摘要： A semiconductor device provided with a replica circuit functioning as an equivalent circuit to that of a path configuration selected as a critical path in the semiconductor circuit and an adjustable delay device for example between an output side of the replica circuit and a phase comparator, the delay value of the delay device being adjustable after production of the chip to a value enabling the replica system including the replica circuit to reliably operate with a margin from the critical path delay of the semiconductor circuit, whereby it becomes possible to prevent setting of an excessive margin and becomes possible to increase the margin when the margin ends up smaller than expected and therefore it becomes possible to flexibly and efficiently configure the replica circuit, and a method of constitution of the same.

    摘要翻译： 一种半导体器件，其具有作为与半导体电路中选择为关键路径的路径配置的等效电路的复制电路，以及例如在复制电路的输出侧和相位比较器之间的可调延迟器件，延迟 延迟器件的值在芯片生产之后可调整到使得包括复制电路的复制系统能够从半导体电路的关键路径延迟可靠地运行的值，从而可以防止设置过大的余量 并且当边缘小于预期时可以增加余量，并且因此可以灵活且有效地配置复制电路及其结构的方法。

    Extramedullary femoral clamp guide system for total knee arthroplasty
    3.
    发明授权
    Extramedullary femoral clamp guide system for total knee arthroplasty 失效
    用于全膝关节置换的髓外股骨夹引导系统

    公开(公告)号：US06258096B1

    公开(公告)日：2001-07-10

    申请号：US09543172

    申请日：2000-04-05

    申请人： Takahiro Seki

    发明人： Takahiro Seki

    IPC分类号： A61B1715

    CPC分类号： A61B17/155

    摘要： An extramedullary femoral clamp guide system enables cutting a portion of the distal end of a femur perpendicularly to an ideal weight bearing axis of the femur as viewed in an antero-posterior image of the femur and cutting the frontal surface of a distal end part of the femur in parallel to the frontal surface of the distal end part of the femur. The extramedullary femoral clamp guide system comprises a first clamp (2) having a pair of holding members (6a, 6b) for clamping a first portion of a distal end part (61) of a femur therebetween, a second clamp having (3) a pair of holding members (11a, 11b) for clamping a second portion of the distal end part (61) of the femur nearer than the first portion of the same to a proximal end of the femur, a connecting mechanism (4) connecting the first and the second clamp (2, 3) so that the first clamp (2) can be translated relative to the second clamp (3), and an extramedullary rod (5) connected to the connecting mechanism (4) so as to extend outside the femur on a straight line passing a middle point between the pair of holding members (6a, 6b) of the first clamp (2) and that between the pair of holding members (11a, 11b) of the second clamp (3).

    摘要翻译： 髓外股骨夹具引导系统能够在股骨的前后图像中观察时切割股骨远端的一部分，该股骨的远端垂直于股骨的理想负重轴线，并切割股骨的远端部分的前表面 股骨平行于股骨远端部的前表面。 髓外股骨夹具引导系统包括第一夹具（2），其具有用于夹持其间的股骨远端部分（61）的第一部分的一对保持构件（6a，6b），第二夹具具有（3） 一对保持构件（11a，11b），用于将股骨的远端部分（61）的第二部分夹持在股骨的近端;连接机构（4），其连接第一 和所述第二夹具（2,3），使得所述第一夹具（2）能够相对于所述第二夹具（3）平移，以及连接到所述连接机构（4）的髓外杆（5），以延伸到所述第二夹具 通过第一夹具（2）的一对保持构件（6a，6b）和第二夹具（3）的一对保持构件（11a，11b）之间的中点的直线上的股骨。

    IMAGE FORMING APPARATUS
    7.
    发明申请
    IMAGE FORMING APPARATUS 有权
    图像形成装置

    公开(公告)号：US20110058831A1

    公开(公告)日：2011-03-10

    申请号：US12878543

    申请日：2010-09-09

    申请人： Motohiro USAMI ,  Takahiro Seki ,  Masashi Nagayama ,  Shinji Aoki ,  Jun Hitosugi

    发明人： Motohiro USAMI ,  Takahiro Seki ,  Masashi Nagayama ,  Shinji Aoki ,  Jun Hitosugi

    IPC分类号： G03G15/00 ,  G03G15/08 ,  G03G15/16 ,  G03G15/043

    CPC分类号： G03G15/1645

    摘要： An apparatus includes: an image carrier; a charger to uniformly charge a surface of the image carrier; an exposing unit to perform write scanning on the image carrier; a developing unit that includes a developer carrier carrying a developer including a toner and that is configured to perform a visible image process on an electrostatic latent image formed on the image carrier; and a transferor to transfer a toner image that has been subjected to the process onto a material. If length Lg of a non-image part directly before an image part in an image carrier moving direction has the relation of Lg≧π·Ds/(Vs/Vp), where Vp and Vs are circumferential velocities of the image carrier and the developer carrier and Ds is a diameter of the developer carrier, suppression of toner attachment on the material is controlled in a predetermined length from an image front end in the direction.

    摘要翻译： 一种装置包括：图像载体; 使图像载体的表面均匀充电的充电器; 曝光单元，用于在所述图像载体上执行写入扫描; 显影单元，其包括携带包含调色剂的显影剂的显影剂载体，其被构造成对形成在所述图像载体上的静电潜像进行可见图像处理; 以及将经过该处理的调色剂图像转印到材料上的转印器。 如果直接在图像载体移动方向上的图像部分之前的非图像部分的长度Lg具有Lg≥＆Pgr;·Ds /（Vs / Vp）的关系，其中Vp和Vs是图像载体的周向速度， 显影剂载体和Ds是显影剂载体的直径，抑制材料上的调色剂附着物从图像前端沿该方向被控制在预定长度。

    Delay control circuit with internal power supply voltage control
    8.
    发明授权
    Delay control circuit with internal power supply voltage control 失效
    延时控制电路具有内部电源电压控制

    公开(公告)号：US06657467B2

    公开(公告)日：2003-12-02

    申请号：US10216318

    申请日：2002-08-12

    申请人： Takahiro Seki ,  Masakatsu Nakai

    发明人： Takahiro Seki ,  Masakatsu Nakai

    IPC分类号： H03L706

    CPC分类号： H03L7/0805 ,  H03K5/133 ,  H03K5/135 ,  H03K5/14 ,  H03K2005/00026 ,  H03K2005/0011 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/0818

    摘要： The present invention provides a semiconductor device a comprising: a delayed-signal-generating circuit for delaying a reference pulse signal by a delay time caused by a delay component on a critical path of a target circuit by a selector included in the delayed signal generating circuit and, thereby, generating a delayed pulse signal; a detection-signal-generating circuit, having the same delay component as the selector, for generating a detection pulse signal delayed in phase by one cycle of a clock signal Ck with respect to the reference pulse signal; a delay-difference-detecting circuit for detecting a phase difference between the delayed pulse signal and the detection pulse signal; and a control circuit for adjusting the magnitude of a power-supply voltage VDD supplied to the target circuit according to the-phase difference detected by the delay-difference-detecting circuit.

    摘要翻译： 本发明提供一种半导体器件a，包括：延迟信号发生电路，用于通过包括在延迟信号发生电路中的选择器将参考脉冲信号延迟由目标电路的关键路径上的延迟分量引起的延迟时间 从而产生延迟的脉冲信号; 检测信号发生电路，具有与选择器相同的延迟分量，用于产生相对于参考脉冲信号相位延迟一个时钟信号Ck的周期的检测脉冲信号; 延迟差检测电路，用于检测延迟脉冲信号和检测脉冲信号之间的相位差; 以及控制电路，用于根据由延迟差检测电路检测的相位差来调整提供给目标电路的电源电压VDD的大小。