公开(公告)号：US5914631A

公开(公告)日：1999-06-22

申请号：US905563

申请日：1997-08-04

申请人： Mitsuo Soneda

发明人： Mitsuo Soneda

IPC分类号： G05F3/24 ,  G05F1/46 ,  G05F1/56 ,  G11C11/407 ,  H03L7/06 ,  G05F1/10

CPC分类号： G05F1/465

摘要： A voltage controlled delay circuit is formed by m number of gates connected in series, phases of a clock signal and a delay signal are compared by a phase comparator, an up signal or a down signal is output, an integrated signal is generated by an integrator, a voltage signal following this is generated by a buffer and fed back as an operating power source voltage to the voltage controlled delay circuit, and further an internal power source voltage following the voltage signal is generated by a buffer and a pMOS transistor, therefore the internal power source voltage of the required lowest limit can be supplied in response to the frequency of the clock and a reduction of the voltage and conservation of the electric power of the LSI circuit can be achieved.

摘要翻译： 电压控制延迟电路由串联连接的m个门，时钟信号和延迟信号的相位由相位比较器进行比较，输出上升信号或下降信号，积分器产生积分信号 ，其后的电压信号由缓冲器产生并作为工作电源电压被反馈到压控延迟电路，并且进一步由缓冲器和pMOS晶体管产生跟随电压信号的内部电源电压，因此， 可以响应于时钟的频率提供所需最低限制的内部电源电压，并且可以实现电压的降低和LSI电路的电力的保护。

公开(公告)号：US5774007A

公开(公告)日：1998-06-30

申请号：US730933

申请日：1996-10-16

申请人： Mitsuo Soneda

发明人： Mitsuo Soneda

IPC分类号： G06F1/10 ,  G11C11/4076 ,  H01L21/822 ,  H01L27/04 ,  H03K5/00 ,  H03K5/13 ,  H03L7/18 ,  H03L7/07

CPC分类号： H03L7/18 ,  G06F1/10 ,  H03K5/133

摘要： A clock distributing apparatus which can decrease the clock skew and can prevent the swing of a signal on clock transmission lines and can achieve a low power consumption, a lower noise of a power supply, and a high speed operation, wherein converts clock signals adjusted in phase to the same phase as a reference clock by a PLL circuit to current signals by voltage/current converters and sends the current signals to clock transmission lines and converts the current signals transmitted to the clock transmission lines to voltage signals by current/voltage converters and sends the voltage signals to circuit blocks of an integrated circuit.

摘要翻译： 一种时钟分配装置，其可以减小时钟偏移并且可以防止时钟传输线上的信号的摆动，并且可以实现低功耗，较低的电源噪声和高速操作，其中转换时钟信号被调整 通过PLL电路与参考时钟相位与电流/电流转换器的电流信号相同，并将电流信号发送到时钟传输线，并将通过电流/电压转换器传输到时钟传输线的电流信号转换为电压信号， 将电压信号发送到集成电路的电路块。

公开(公告)号：US4447812A

公开(公告)日：1984-05-08

申请号：US384560

申请日：1982-06-03

申请人： Mitsuo Soneda ,  Takaji Ohtsu

发明人： Mitsuo Soneda ,  Takaji Ohtsu

IPC分类号： H04N5/66 ,  G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  H04N3/12 ,  G09G3/18

CPC分类号： G09G3/3688 ,  G09G3/3648 ,  H04N3/127 ,  G09G2310/0297 ,  G09G3/2011

摘要： A liquid crystal matrix display device has a plurality of display elements arranged in an X-Y matrix pattern. Vertical transmitting lines are connected to all of the display elements of each column, and horizontal transmitting lines are connected to each of the display elements of each row. Each of the vertical lines is connected through an input switching element to an input circuit to receive a video input signal and a horizontal pulse generator provides sequential pulse signals to control terminals of the input switching elements. In order to improve the resolution without sacrifice of contrast, the vertical transmitting lines are arranged into groups of a predetermined number of such lines, and the input switching elements associated with the lines of each such group have their control electrodes coupled together to a respective output of the horizontal scanning pulse generator. The input circuit includes time-demultiplexing circuitry, for example, formed of sample/hold circuits, to present respective sampled versions of the input signal, staggered with respect to one another, to input electrodes of respective ones of the input switching devices of each of the groups.

摘要翻译： 液晶矩阵显示装置具有以X-Y矩阵图案排列的多个显示元件。 垂直传输线连接到每列的所有显示元件，并且水平传输线连接到每行的每个显示元件。 每个垂直线通过输入开关元件连接到输入电路以接收视频输入信号，并且水平脉冲发生器向输入开关元件的控制端提供顺序脉冲信号。 为了在不牺牲对比度的情况下提高分辨率，垂直传输线被布置成预定数量的这样的线的组，并且与每个这样的组的线相关联的输入开关元件的控制电极耦合到相应的输出 的水平扫描脉冲发生器。 输入电路包括例如由采样/保持电路形成的时分解复用电路，以将相对于彼此交错的输入信号的相应采样版本呈现给每个的各个输入开关装置的输入电极 团体。

公开(公告)号：US07355214B2

公开(公告)日：2008-04-08

申请号：US10752705

申请日：2004-01-08

申请人： Takashi Noguchi ,  Mitsuo Soneda

发明人： Takashi Noguchi ,  Mitsuo Soneda

IPC分类号： H01L31/0328

CPC分类号： H01L21/823814 ,  H01L21/823807

摘要： A method for forming a Field Effect Transistor (FET) within a strain effect semiconductor layer is disclosed, whereby the source and drain of the FET are formed only in the strain effect silicon layer. The FET may be formed as a gate electrode of a p-channel type field effect transistor, and a gate electrode of a n-channel type field effect transistor on the silicon layer which has the strain effect through a gate insulating film. The sources and drains of p- and n-type diffusion layers are then formed in the silicon layer having the strain effect, on both sides of the gate electrode.

摘要翻译： 公开了一种在应变效应半导体层内形成场效应晶体管（FET）的方法，由此仅在应变效应硅层中形成FET的源极和漏极。 FET可以形成为p沟道型场效应晶体管的栅极电极和在硅层上的n沟道型场效应晶体管的栅极，其通过栅极绝缘膜具有应变效应。 然后在具有应变效应的硅层中，在栅电极的两侧形成p型和n型扩散层的源极和漏极。

公开(公告)号：US5545941A

公开(公告)日：1996-08-13

申请号：US489714

申请日：1995-06-13

申请人： Mitsuo Soneda ,  Takahiro Seki

发明人： Mitsuo Soneda ,  Takahiro Seki

IPC分类号： H03B5/32 ,  H03B5/36 ,  H03K3/013 ,  H03K3/354

CPC分类号： H03K3/3545 ,  H03K3/013

摘要： A crystal oscillator circuit including a quartz vibrator; an inverter circuit connected in parallel to the quartz vibrator and comprised of at least two transistors connected at their output ends to a first power-supply potential or a second power-supply potential lower than the first power-supply potential; a first current mirror circuit, with one current input-output end connected to a connection line with the inverter circuit of the first power-supply potential, the other current input-output end connected to the output end of the oscillator circuit; and either a second current mirror circuit having two current input-output ends, one current input-output end connected to a connection line with the inverter circuit of the second power-supply potential, the other current input-output end connected to the output end of the oscillator circuit, current flowing to one current input-output end, current flowing to the other current input-output end, and the level of the output end of the oscillator circuit being shifted to the level of the second power-supply potential when the output end of the inverter circuit is connected to the second power-supply potential or a circuit for shifting the level of the output end of the inverter circuit to the level of a second power-supply potential in accordance with the level of the input end of the inverter circuit when the output end of the circuit is connected to a second power-supply potential.

摘要翻译： 一种包括石英振子的晶体振荡器电路; 与石英振子并联连接的逆变器电路，由至少两个在其输出端连接到第一电源电位或低于第一电源电位的第二电源电位的晶体管; 第一电流镜电路，其一个电流输入输出端连接到与第一电源电位的反相器电路的连接线，另一个电流输入 - 输出端连接到振荡器电路的输出端; 以及具有两个电流输入 - 输出端的第二电流镜电路，一个电流输入 - 输出端连接到与第二电源电位的反相器电路的连接线，另一个电流输入 - 输出端连接到输出端 的振荡器电路，流向一个电流输入 - 输出端的电流，流向另一个电流输入 - 输出端的电流，以及振荡器电路的输出端的电平被移动到第二电源电位的电平，当 逆变器电路的输出端连接到第二电源电位或用于根据输入端的电平将逆变器电路的输出端的电平转换到第二电源电位的电平的电路 的电路的输出端连接到第二电源电位。

公开(公告)号：US4803480A

公开(公告)日：1989-02-07

申请号：US871427

申请日：1986-05-12

申请人： Mitsuo Soneda ,  Yoshikazu Hazama

发明人： Mitsuo Soneda ,  Yoshikazu Hazama

IPC分类号： H04N5/66 ,  G02F1/133 ,  G09G3/36

CPC分类号： G09G3/3618

摘要： According to the present invention, in a liquid crystal display apparatus, there are provided second horizontal switching elements M.sub.Bl to M.sub.Bm, which are driven at the advanced phase relative to picture element switching signals .phi..sub.Hl to .phi..sub.Hm, at columns L.sub.l to L.sub.m to which a video signal is supplied, a signal, which is derived through said second horizontal switching elements M.sub.Bl to M.sub.Bm, is fed back through an inverting circuit (14) and the like to an input terminal (1), and there are provided third switching elements M.sub.Rl to M.sub.Rm which are turned on at every predetermined period. According to this apparatus, since a signal derived from a liquid crystal cell C is returned to the same liquid crystal cell C, the displacement of the picture and the like can be avoided, any special scanning and the like are not required and a prior art driving circuit and so on can be used as they are. Further, since the potential of the signal line is reset at every predetermined period, it is possible to prevent the quality of the picture from being deteriorated by a residual charge and the like and the excellent display of a still picture can be carried out over a long time period.

摘要翻译： PCT No.PCT / JP85 / 00508 Sec。 371日期：1986年5月12日 102（e）日期1986年5月12日PCT提交1985年9月12日PCT公布。 出版物WO86 / 01926 根据本发明，在液晶显示装置中，设置有第二水平切换元件MB1〜MBm，它们相对于像素切换信号ph1H1至ph1Hm以超前相位驱动， 在提供视频信号的列L1至Lm的列中，通过所述第二水平切换元件MB1至MBm导出的信号通过反相电路（14）等反馈到输入端（1）， 并且设置有在每个预定周期被接通的第三开关元件MR1至MRm。 根据该装置，由于来自液晶单元C的信号返回到相同的液晶单元C，因此可以避免图像的位移等，不需要任何特殊的扫描等，现有技术 驱动电路等可以直接使用。 此外，由于信号线的电位在每个预定周期被复位，所以可以防止图像的质量由于剩余电荷等而劣化，并且静止图像的优异显示可以通过 长时间

公开(公告)号：US4694341A

公开(公告)日：1987-09-15

申请号：US826019

申请日：1986-02-04

申请人： Mitsuo Soneda ,  Yoshikazu Hazama

发明人： Mitsuo Soneda ,  Yoshikazu Hazama

IPC分类号： G11C27/02 ,  H04N5/44

CPC分类号： G11C27/024

摘要： A sample-and-hold circuit is provided wherein an input signal is fed via a first gate element to one end of a first capacitor whose other end is alternately grounded, the one end of the first capacitor being connected via a second capacitor to a gate (or base) of a source (or emitter) follower transistor to obtain an output from the source (or emitter) of the transistor which is connected via a second gate element to one end of the first capacitor, while the gate (or base) of the transistor is connected via a third gate element to a DC voltage supply having a predetermined voltage value, and the second and third gate elements are turned on during a first period of the input signal so that a voltage corresponding to the gate-source (or base-emitter) offset voltage of the transistor is stored in the second capacitor, while the first gate element is turned on during a second period of the input signal to produce an output signal equivalent in level to the input signal.

摘要翻译： 提供了采样保持电路，其中输入信号经由第一栅极元件馈送到第一电容器的另一端交替接地的一端，第一电容器的一端经由第二电容器连接到栅极 （或发射极）跟随器晶体管的（或基极），以获得来自经由第二栅极元件连接到第一电容器的一端的晶体管的源极（或发射极）的输出，而栅极（或基极） 的晶体管通过第三栅极元件连接到具有预定电压值的直流电压源，并且第二和第三栅极元件在输入信号的第一周期期间导通，使得对应于栅极源（ 或基极 - 发射极）的晶体管的偏移电压存储在第二电容器中，而第一栅极元件在输入信号的第二周期期间导通，以产生与输入信号等级的输出信号。

公开(公告)号：US4578597A

公开(公告)日：1986-03-25

申请号：US552036

申请日：1983-11-02

申请人： Mitsuo Soneda ,  Manami Fukuzawa ,  Takaji Ohtsu

发明人： Mitsuo Soneda ,  Manami Fukuzawa ,  Takaji Ohtsu

IPC分类号： H03K19/094 ,  G11C19/00 ,  G11C19/28 ,  H03K5/02 ,  H03K5/135 ,  H03K5/153 ,  H03K5/26 ,  H03K19/096 ,  H03K3/017 ,  H03K5/04

CPC分类号： H03K19/096 ,  H03K5/135 ,  H03K5/153 ,  H03K5/26

摘要： A pulse generating circuit comprises a first series connection of a first switching element (3:13) and a second switching element (4), a second series connection of a capacitive element (5) and a third switching element (6) coupled with a connecting point between the first and second switching elements, an amplifying element (7) having input and output terminals connected to both ends of the capacitive element (5), respectively, and a fourth switching element (8) connected to the output end of the amplifying element (7), and is supplied with a first input signal varying in level through the control terminals of the first and third switching elements (3:13, 6) and a second input signal varying in level through the control terminals of the second and fourth switching elements (4, 8), thereby to obtain a pulse having the width corresponding to the time interval from a variation in the level of the first input signal to a variation in the level of the second input signal at the output end of the amplifying element (7).

摘要翻译： PCT No.PCT / JP83 / 00068 Sec。 371日期：1983年11月2日 102（e）1983年11月2日日期PCT提交1983年3月5日PCT公布。 公开号WO83 / 03174 日期：1983年9月15日。脉冲发生电路包括第一开关元件（3:13）和第二开关元件（4）的第一串联连接，电容元件（5）和第三开关 元件（6）与第一和第二开关元件之间的连接点耦合，具有分别连接到电容元件（5）的两端的输入和输出端子的放大元件（7）和第四开关元件（8） 连接到放大元件（7）的输出端，并且被提供有通过第一和第三开关元件（3:13,6）的控制端子电平变化的第一输入信号和在电平上变化的第二输入信号 通过第二和第四开关元件（4,8）的控制端子，从而获得具有对应于从第一输入信号的电平的变化到第二开关元件的电平变化的时间间隔的宽度的脉冲 输入信号 在放大元件（7）的输出端。

公开(公告)号：US4314162A

公开(公告)日：1982-02-02

申请号：US109336

申请日：1980-01-03

申请人： Takao Tsuchiya ,  Mitsuo Soneda

发明人： Takao Tsuchiya ,  Mitsuo Soneda

IPC分类号： G11C27/04 ,  G11C19/28 ,  G11C27/00 ,  H01L21/339 ,  H01L29/76 ,  H01L29/762 ,  H01L29/772 ,  H03H7/30 ,  H03H15/02 ,  H03K5/00 ,  H03K17/60

CPC分类号： H03H15/02 ,  G11C19/28 ,  G11C27/00 ,  H01L29/76

摘要： A filter circuit of the type utilizing a charge-transfer device, such as a bucket brigade device, comprises a clocking signal drive circuit for supplying a clocking signal; a clock signal generator at whose output a clocking control signal is provided; a transistor whose base is connected to the output of the clock signal generator; a plurality of successive capacitive storage stages for sequentially holding a charge level representing a time-sampled input signal, each of the capacitive storage stages having a clocking electrode for receiving the clocking signal so that the charge level is transferred from one to another of the capacitive storage stages in succession, and at least one of the capacitive storage stages being formed of first and second parallel-connected capacitive circuit portions, and the first and second capacitive circuit portions having respective clocking electrodes coupled to the clock signal generator and to the emitter of the transistor, respectively; and a current feedback circuit, such as a current mirror circuit, for detecting the current flowing through the collector of the transistor and applying a corresponding current to a capacitive storage stage in advance of that stage which is coupled to the emitter of the transistor.

摘要翻译： 利用诸如铲斗旅装置的电荷转移装置的类型的滤波器电路包括用于提供时钟信号的时钟信号驱动电路; 时钟信号发生器，其输出提供时钟控制信号; 其基极连接到时钟信号发生器的输出的晶体管; 多个连续的电容性存储级，用于顺序地保持表示时间采样的输入信号的电荷电平，每个电容性存储级具有用于接收时钟信号的时钟电极，使得充电电平从电容 存储级，并且电容性存储级中的至少一个由第一和第二并联电容电路部分形成，并且第一和第二电容电路部分具有耦合到时钟信号发生器和与时钟信号发生器的发射极 晶体管; 以及电流反馈电路，例如电流镜电路，用于检测流过晶体管的集电极的电流，并在耦合到晶体管的发射极的该级之前将电流施加到电容性存储级。

公开(公告)号：US08094491B2

公开(公告)日：2012-01-10

申请号：US12230283

申请日：2008-08-27

申请人： Makoto Kitagawa ,  Mitsuo Soneda

发明人： Makoto Kitagawa ,  Mitsuo Soneda

IPC分类号： G11C11/39

CPC分类号： G11C11/39

摘要： A semiconductor device includes a memory cell including a thyristor element with a gate having a pnpn structure formed in a semiconductor substrate, and a plurality of access transistors formed on the semiconductor substrate and each connected at a first terminal thereof to a storage node at one terminal of the thyristor element such that a potential at the storage node can be transmitted to bit lines different from each other, the gate of the thyristor element and the gates of the plurality of access transistors of the memory cell being connected to word lines different from one another.

摘要翻译： 一种半导体器件包括：存储单元，具有在半导体衬底中形成有pnpn结构的栅极的晶闸管元件和形成在半导体衬底上并分别在其第一端部连接到一个端子处的存储节点的多个存取晶体管 的晶闸管元件，使得存储节点处的电位可以传输到彼此不同的位线，晶闸管元件的栅极和存储单元的多个存取晶体管的栅极连接到不同于一个的字线 另一个。