公开(公告)号：US08710484B2

公开(公告)日：2014-04-29

申请号：US13580401

申请日：2011-02-23

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC分类号： H01L47/00

CPC分类号： H01L45/1226 ,  G11C13/0002 ,  G11C2213/77 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1633

摘要： A manufacturing method for manufacturing, with a simple process, a non-volatile memory apparatus having a stable memory performance includes: (a) forming a stacking-structure body above a substrate by alternately stacking conductive layers comprising a transition metal and interlayer insulating films comprising an insulating material; (b) forming a contact hole penetrating through the stacking-structure body to expose part of each of the conductive layers; (c) forming variable resistance layers by oxidizing the part of each of the conductive layers, the part being exposed in the contact hole, and each of the variable resistance layers having a resistance value that reversibly changes according to an application of an electric signal; and (d) forming a pillar electrode in the contact hole by embedding a conductive material in the contact hole, the pillar electrode being connected to each of the variable resistance layers.

摘要翻译： 一种以简单的工艺制造具有稳定的存储性能的非易失性存储装置的制造方法包括：（a）通过交替堆叠包括过渡金属和层间绝缘膜的导电层，在衬底上形成堆叠结构体，所述导电层包括： 绝缘材料; （b）形成穿过堆叠结构体的接触孔，以暴露出每个导电层的一部分; （c）通过氧化每个导电层的一部分形成可变电阻层，该部分暴露在接触孔中，并且每个可变电阻层具有根据电信号的应用可逆地改变的电阻值; 和（d）通过在接触孔中埋设导电材料而在接触孔中形成柱状电极，该柱状电极与各可变电阻层连接。

公开(公告)号：US08422268B2

公开(公告)日：2013-04-16

申请号：US12677413

申请日：2009-05-01

申请人： Koji Arita ,  Takumi Mikawa ,  Mitsuteru Iijima ,  Takashi Okada

发明人： Koji Arita ,  Takumi Mikawa ,  Mitsuteru Iijima ,  Takashi Okada

IPC分类号： G11C11/34 ,  G11C11/36 ,  H01L29/12

CPC分类号： H01L27/101 ,  H01L27/24 ,  H01L45/00

摘要： A memory element (3) arranged in matrix in a memory device and including a resistance variable element (1) which switches its electrical resistance value in response to a positive or negative electrical pulse applied thereto and retains the switched electrical resistance value; and a current control element (2) for controlling a current flowing when the electrical pulse is applied to the resistance variable element (1); wherein the current control element (2) includes a first electrode; a second electrode; and a current control layer sandwiched between the first electrode and the second electrode; and wherein the current control layer comprises SiNx, and at least one of the first electrode and the second electrode comprises α-tungsten.

摘要翻译： 一种存储元件（3），其以矩阵形式布置在存储器件中，并且包括响应于施加到其上的正或负电脉冲而切换其电阻值的电阻可变元件（1），并保持所述开关电阻值; 以及电流控制元件（2），用于控制当电脉冲施加到电阻可变元件（1）时流动的电流; 其中所述电流控制元件（2）包括第一电极; 第二电极; 以及夹在所述第一电极和所述第二电极之间的电流控制层; 并且其中所述电流控制层包括SiN x，并且所述第一电极和所述第二电极中的至少一个包括α-钨。

公开(公告)号：US20110164447A1

公开(公告)日：2011-07-07

申请号：US13061312

申请日：2009-09-17

申请人： Koji Arita ,  Takumi Mikawa ,  Mitsuteru Iijima ,  Kenji Tominaga

发明人： Koji Arita ,  Takumi Mikawa ,  Mitsuteru Iijima ,  Kenji Tominaga

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： A current steering element which can prevent occurrence of write disturb even when electric pulses having different polarities are applied and can cause large current to flow through a variable resistance element, and with which data can be written without problem. In a storage element (3) including: a variable resistance element (1) whose electric resistance value changes in response to application of electric pulses having a positive polarity and a negative polarity and which maintains the changed electric resistance value; and the current steering element (2) that steers current flowing through the variable resistance element (1) when the electric pulses are applied, the current steering element (2) includes: a first electrode (32); a second electrode (31); and a current steering layer (33) interposed between the first electrode (32) and the second electrode (31). When the current steering layer (33) includes SiNx (0

摘要翻译： 即使施加具有不同极性的电脉冲也能够防止写入干扰的发生，并且可能导致大的电流流过可变电阻元件并且可以无限制地写入数据的电流导向元件。 在一种存储元件（3）中，包括：可变电阻元件（1），其电阻值响应于具有正极性和负极性的电脉冲的应用而改变并且保持改变的电阻值; 以及当施加电脉冲时转向流过可变电阻元件（1）的电流的当前操舵元件（2），所述电流操舵元件（2）包括：第一电极（32）; 第二电极（31）; 和介于所述第一电极（32）和所述第二电极（31）之间的电流转向层（33）。 当电流导向层（33）包括SiNx（0

公开(公告)号：US20110103132A1

公开(公告)日：2011-05-05

申请号：US13000243

申请日：2010-04-22

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L27/24

摘要： Provided are a nonvolatile memory element which is capable of effectively preventing an event that when a failure occurs in a certain nonvolatile memory element, data cannot be written to and read from another nonvolatile memory element belonging to the same column or row as that to which the nonvolatile memory element in a failed state belongs, and a semiconductor memory device including the nonvolatile memory element.A nonvolatile memory element comprises a current controlling element (112) having a non-linear current-voltage characteristic, a resistance variable element (105) which changes reversibly between a low-resistance state and a high-resistance state in which a resistance value of the resistance variable element is higher than a resistance value of the resistance variable element in the low-resistance state, in response to voltage pulses applied, and a fuse (103), the current controlling element (112), the resistance variable element (105) and the fuse (103) being connected in series, and the fuse (103) being configured to be blown when the current controlling element (112) is substantially short-circuited.

摘要翻译： 提供了一种非易失性存储元件，其能够有效地防止当在某个非易失性存储元件中发生故障时的事件，不能将数据写入和读取与属于同一列或列的另一非易失性存储器元件 处于故障状态的非易失性存储元件属于非易失性存储元件，以及包括非易失性存储元件的半导体存储器件。 非易失性存储元件包括具有非线性电流 - 电压特性的电流控制元件（112），在低电阻状态和高电阻状态之间可逆地改变的电阻可变元件（105），其中电阻值 电阻可变元件响应于施加的电压脉冲而高于低电阻状态下的电阻可变元件的电阻值，以及熔丝（103），电流控制元件（112），电阻可变元件（105） ）和保险丝（103）串联连接，并且熔断器（103）被配置为当电流控制元件（112）基本上短路时被断开。

公开(公告)号：US07026687B2

公开(公告)日：2006-04-11

申请号：US10387427

申请日：2003-03-14

申请人： Satoshi Shinozaki ,  Mitsuteru Iijima ,  Hideo Kurihara

发明人： Satoshi Shinozaki ,  Mitsuteru Iijima ,  Hideo Kurihara

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： A proposed non-volatile semiconductor memory and a method of manufacturing the same are directed to performing stable and highly reliable operations. First, grooves are formed in a p-type silicon semiconductor substrate, and impurity diffusion layers are formed on the bottom surfaces of the grooves. A gate insulating film is then formed on the p-type silicon semiconductor substrate. This gate insulating film has a three-layer structure in which a first insulating film made of a silicon oxide film, a charge capturing film made of a silicon nitride film, and a second insulating film made of a silicon oxide film, are laminated in this order. A gate electrode is then formed on the gate insulating film. A convexity formed by the grooves serves as the channel region of the non-volatile semiconductor memory. Even if the device size is reduced, an effective channel length can be secured in this non-volatile semiconductor memory. Thus, excellent stability and reliability can be achieved.

公开(公告)号：US06750520B2

公开(公告)日：2004-06-15

申请号：US10085023

申请日：2002-03-01

申请人： Hideo Kurihara ,  Mitsuteru Iijima ,  Kiyoshi Itano ,  Tetsuya Chida

发明人： Hideo Kurihara ,  Mitsuteru Iijima ,  Kiyoshi Itano ,  Tetsuya Chida

IPC分类号： H01L2976

CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/7923

摘要： A nonvolatile semiconductor memory comprises a pair of diffused layers formed in the surface area of a p-type silicon substrate, and a gate electrode (polysilicon film and tungsten silicide film formed on a gate oxide between the diffused layers over the p-type silicon substrate. Silicon nitride film is formed at both ends of the gate oxide so that the carrier trap characteristic may become high locally in areas near the pair of diffused layer. This configuration prevents carrier injection to other than the ends of the gate oxide, ensures reliable recording and storage, and increases reliability by preventing write and erase error.

摘要翻译： 非易失性半导体存储器包括形成在p型硅衬底的表面区域中的一对扩散层，以及形成在p型硅衬底上的扩散层之间的栅极氧化物上的栅电极（多晶硅膜和硅化钨膜） 在栅极氧化物的两端形成氮化硅膜，使得载流子阱特性在一对扩散层附近的区域局部变高，这样可以防止载流子注入到栅极氧化物的末端以外，确保可靠的记录 并存储，并通过防止写入和擦除错误提高可靠性。

公开(公告)号：US08339835B2

公开(公告)日：2012-12-25

申请号：US13000243

申请日：2010-04-22

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L27/24

摘要： A nonvolatile memory element includes a current controlling element having a non-linear current-voltage characteristic, a resistance variable element which changes reversibly between a low-resistance state and a high-resistance state in which a resistance value of the resistance variable element is higher than a resistance value of the resistance variable element in the low-resistance state, in response to voltage pulses applied, and a fuse. The current controlling element, the resistance variable element and the fuse are connected in series, and the fuse is configured to be blown when the current controlling element is substantially short-circuited.

摘要翻译： 非易失性存储元件包括具有非线性电流 - 电压特性的电流控制元件，在电阻可变元件的电阻值较高的低电阻状态与高电阻状态之间可逆地改变的电阻可变元件 比电阻可变元件在低电阻状态下的电阻值，响应于施加的电压脉冲和保险丝。 电流控制元件，电阻可变元件和保险丝串联连接，并且当电流控制元件基本上短路时，保险丝被配置为被熔断。

公开(公告)号：US20120319072A1

公开(公告)日：2012-12-20

申请号：US13580401

申请日：2011-02-23

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L45/1226 ,  G11C13/0002 ,  G11C2213/77 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1633

摘要： A manufacturing method for manufacturing, with a simple process, a non-volatile memory apparatus having a stable memory performance includes: (a) forming a stacking-structure body above a substrate by alternately stacking conductive layers comprising a transition metal and interlayer insulating films comprising an insulating material; (b) forming a contact hole penetrating through the stacking-structure body to expose part of each of the conductive layers; (c) forming variable resistance layers by oxidizing the part of each of the conductive layers, the part being exposed in the contact hole, and each of the variable resistance layers having a resistance value that reversibly changes according to an application of an electric signal; and (d) forming a pillar electrode in the contact hole by embedding a conductive material in the contact hole, the pillar electrode being connected to each of the variable resistance layers.

摘要翻译： 一种以简单的工艺制造具有稳定的存储性能的非易失性存储装置的制造方法包括：（a）通过交替堆叠包括过渡金属和层间绝缘膜的导电层，在衬底上形成堆叠结构体，所述导电层包括： 绝缘材料; （b）形成穿过堆叠结构体的接触孔，以暴露出每个导电层的部分; （c）通过氧化每个导电层的一部分形成可变电阻层，该部分暴露在接触孔中，并且每个可变电阻层具有根据电信号的应用可逆地改变的电阻值; 和（d）通过在接触孔中埋设导电材料而在接触孔中形成柱状电极，该柱状电极与各可变电阻层连接。

公开(公告)号：US08320159B2

公开(公告)日：2012-11-27

申请号：US12993706

申请日：2010-03-15

申请人： Zhiqiang Wei ,  Ryotaro Azuma ,  Takeshi Takagi ,  Mitsuteru Iijima ,  Yoshihiko Kanzawa

发明人： Zhiqiang Wei ,  Ryotaro Azuma ,  Takeshi Takagi ,  Mitsuteru Iijima ,  Yoshihiko Kanzawa

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/115 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： Each of memory cells (MC) includes one transistor and one resistance variable element. The transistor includes a first main terminal, a second main terminal and a control terminal. The resistance variable element includes a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode. A first main terminal of one of two adjacent memory cells is connected to a second main terminal of the other memory cell, to form a series path (SP) sequentially connecting main terminals of the plurality of memory cells in series. Each of the memory cells is configured such that the control terminal is a part of a first wire (WL) associated with the memory cell or is connected to the first wire associated with the memory cell, the second electrode is a part of a second wire (SL) associated with the memory cell or is connected to the second wire associated with the memory cell; and the first electrode is a part of a series path (SP) associated with the memory cell or is connected to the series path associated with the memory cell.

摘要翻译： 每个存储单元（MC）包括一个晶体管和一个电阻可变元件。 晶体管包括第一主端子，第二主端子和控制端子。 电阻可变元件包括设置在第一电极和第二电极之间的第一电极，第二电极和电阻变化层。 两个相邻存储单元之一的第一主端子连接到另一个存储单元的第二主端子，以形成串联连接多个存储单元的主端子的串行路径（SP）。 每个存储器单元被配置为使得控制端子是与存储器单元相关联的第一布线（WL）的一部分或者连接到与存储单元相关联的第一布线，第二电极是第二布线 （SL），或者连接到与存储器单元相关联的第二线; 并且第一电极是与存储器单元相关联的或连接到与存储器单元相关联的串联路径的串联路径（SP）的一部分。

公开(公告)号：US08295123B2

公开(公告)日：2012-10-23

申请号：US12669174

申请日：2008-07-11

申请人： Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

发明人： Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

IPC分类号： G11C13/00

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L45/00

摘要： In a current rectifying element (10), a barrier height φA of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height φB of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1

摘要翻译： 在电流整流元件（10）中，阻挡层（11）在其厚度方向上的中心区域（14）的阻挡高度＆amp; A被夹在第一电极层（12）和第二电极层（13）之间 ）形成为大于阻挡层（11）和第一电极层（12）之间的界面（17）附近的区域和阻挡层（17）之间的界面（17）的势垒高度B （11）和第二电极层（13）。 阻挡层（11）具有例如阻挡层（11a），（11b）和（11c）的三层结构。 阻挡层（11a），（11b）和（11c）例如由SiNx2，SiNx1和SiNx1（X1