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    TRI-GATE TRANSISTORS AND METHODS TO FABRICATE SAME
    2.
    发明申请
    TRI-GATE TRANSISTORS AND METHODS TO FABRICATE SAME 审中-公开
    三栅晶体管及其制造方法

    公开(公告)号：US20070262389A1

    公开(公告)日：2007-11-15

    申请号：US11828290

    申请日：2007-07-25

    申请人： Robert Chau ,  Suman Datta ,  Brian Doyle ,  Been-Yih Jin

    发明人： Robert Chau ,  Suman Datta ,  Brian Doyle ,  Been-Yih Jin

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. The trench is then filled with a semiconductor material. The semiconductor material is then planarized with the remainder of the oxide layer and the remainder of the oxide layer is then removed. The semiconductor fins thus exposed are of uniform height to within a specified tolerance.

    摘要翻译： 本发明的实施例提供了一种用于对绝缘体上硅晶体管制造实现均匀的硅体高度的方法。 对于一个实施例，在半导体衬底上设置牺牲氧化物层。 氧化层被蚀刻以形成沟槽。 然后用半导体材料填充沟槽。 然后将半导体材料与氧化物层的其余部分平坦化，然后除去氧化物层的其余部分。 这样暴露的半导体鳍片具有均匀的高度，在规定的公差范围内。

    Methods of forming nanodots using spacer patterning techniques and structures formed thereby
    4.
    发明授权
    Methods of forming nanodots using spacer patterning techniques and structures formed thereby 失效
    使用间隔图案化技术和由此形成的结构形成纳米点的方法

    公开(公告)号：US08388854B2

    公开(公告)日：2013-03-05

    申请号：US11968091

    申请日：2007-12-31

    申请人： Brian Doyle ,  Been-Yih Jin ,  Jack Kavalieros ,  Robert Chau

    发明人： Brian Doyle ,  Been-Yih Jin ,  Jack Kavalieros ,  Robert Chau

    IPC分类号： C23F1/00

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  Y10T428/24612

    摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a first block on a nanodot material, forming a first spacer on the first block, removing the first block to form a free standing spacer, removing exposed portions of the nanodot material and then the free standing spacer to form nanowires, forming a second block at an angle to a length of the nanowires, forming a second spacer on the second block, forming a second free standing spacer on the nanowires by removing the second block, and removing exposed portions of the nanowires and then the second free standing spacer to form an ordered array of nanodots.

    摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括在纳点物质上形成第一块，在第一块上形成第一间隔物，去除第一块以形成自由间隔物，去除纳米点材料的暴露部分，然后除去自由基间隔物以形成纳米线， 在与所述纳米线的长度成一定角度地形成第二块，在所述第二块上形成第二间隔物，通过去除所述第二块在所述纳米线上形成第二自由间隔物，以及去除所述纳米线的暴露部分，然后除去所述第二自由基 形成有序阵列的纳米点。

    Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned SI to SIGE conversion processes and structures formed thereby
    5.
    发明授权
    Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned SI to SIGE conversion processes and structures formed thereby 有权
    通过自对准SI将SIGNA转换过程和结构形成的多晶纳米级晶体管中的单轴应变的方法

    公开(公告)号：US08288233B2

    公开(公告)日：2012-10-16

    申请号：US11864726

    申请日：2007-09-28

    申请人： Been-Yih Jin ,  Brian Doyle ,  Jack Kavalieros ,  Suman Datta

    发明人： Been-Yih Jin ,  Brian Doyle ,  Jack Kavalieros ,  Suman Datta

    IPC分类号： H01L21/8244

    CPC分类号： H01L29/7851 ,  H01L29/66795 ,  H01L29/7848

    摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods may include providing a gate electrode comprising a top surface and first and second laterally opposite sidewalls, wherein a hard mask is disposed on the top surface, a source drain region disposed on opposite sides of the gate electrode, and a spacer disposed on the first and second laterally opposed sidewalls of the gate electrode, forming a silicon germanium layer on exposed portions of the top surface and the first and second laterally opposite sidewalls of the source drain region and then oxidizing a portion of the silicon germanium layer, wherein a germanium portion of the silicon germanium layer is forced down into the source drain region to convert a silicon portion of the source drain region into a silicon germanium portion of the source drain region.

    摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例可以包括提供包括顶表面和第一和第二横向相对的侧壁的栅电极，其中硬掩模设置在顶表面上，源极漏极区域设置在栅电极的相对侧上， 在栅电极的第一和第二横向相对的侧壁上，在源漏区的顶表面和第一和第二横向相对的侧壁的暴露部分上形成硅锗层，然后氧化硅锗层的一部分，其中 硅锗层的锗部分被迫下降到源极漏极区域中，以将源极区域的硅部分转换成源极漏极区域的硅锗部分。

    Methods for inducing strain in non-planar transistor structures
    7.
    发明授权
    Methods for inducing strain in non-planar transistor structures 有权
    在非平面晶体管结构中诱导应变的方法

    公开(公告)号：US07709312B2

    公开(公告)日：2010-05-04

    申请号：US11540863

    申请日：2006-09-29

    申请人： Been-Yih Jin ,  Brian Doyle ,  Uday Shah ,  Jack Kavalieros

    发明人： Been-Yih Jin ,  Brian Doyle ,  Uday Shah ,  Jack Kavalieros

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

    摘要： Methods for inducing compressive strain in channel region of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include forming trenches in a semiconductor body adjacent to gate structure spacers. The semiconductor body can be situated on a substrate and in a different plane relative to the substrate. The gate structure can be situated on the semiconductor body and the silicon fin and perpendicular to the semiconductor body. After formation of the semiconductor body and the gate structure on the substrate, a dielectric material can be conformally deposited on the substrate and etched to form spacers on the semiconductor body and the gate structure. The substrate can be patterned and etched to form trenches in the semiconductor body adjacent to the spacers on the gate structure. A strain material can be introduced into the trenches.

    摘要翻译： 用于在非平面晶体管的沟道区域中诱导压缩应变的方法以及通过这种方法形成的器件和系统。 在一个实施例中，一种方法可以包括在与栅极结构间隔物相邻的半导体本体中形成沟槽。 半导体本体可以位于衬底上并且在相对于衬底的不同平面中。 栅极结构可以位于半导体本体和硅片上并且垂直于半导体本体。 在衬底上形成半导体本体和栅极结构之后，电介质材料可以共形沉积在衬底上并被蚀刻以在半导体本体和栅极结构上形成间隔物。 可以对衬底进行图案化和蚀刻，以在与栅极结构上的间隔物相邻的半导体本体中形成沟槽。 可以将应变材料引入到沟槽中。

    Methods for inducing strain in non-planar transistor structures
    8.
    发明申请
    Methods for inducing strain in non-planar transistor structures 有权
    在非平面晶体管结构中诱导应变的方法

    公开(公告)号：US20080079094A1

    公开(公告)日：2008-04-03

    申请号：US11540863

    申请日：2006-09-29

    申请人： Been-Yih Jin ,  Brian Doyle ,  Uday Shah ,  Jack Kavalieros

    发明人： Been-Yih Jin ,  Brian Doyle ,  Uday Shah ,  Jack Kavalieros

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

    摘要： Methods for inducing compressive strain in channel region of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include forming trenches in a semiconductor body adjacent to gate structure spacers. The semiconductor body can be situated on a substrate and in a different plane relative to the substrate. The gate structure can be situated on the semiconductor body and the silicon fin and perpendicular to the semiconductor body. After formation of the semiconductor body and the gate structure on the substrate, a dielectric material can be conformally deposited on the substrate and etched to form spacers on the semiconductor body and the gate structure. The substrate can be patterned and etched to form trenches in the semiconductor body adjacent to the spacers on the gate structure. A strain material can be introduced into the trenches.

    摘要翻译： 用于在非平面晶体管的沟道区域中诱导压缩应变的方法以及通过这种方法形成的器件和系统。 在一个实施例中，一种方法可以包括在与栅极结构间隔物相邻的半导体本体中形成沟槽。 半导体本体可以位于衬底上并且在相对于衬底的不同平面中。 栅极结构可以位于半导体本体和硅片上并且垂直于半导体本体。 在衬底上形成半导体本体和栅极结构之后，电介质材料可以共形沉积在衬底上并被蚀刻以在半导体本体和栅极结构上形成间隔物。 可以对衬底进行图案化和蚀刻，以在与栅极结构上的间隔物相邻的半导体本体中形成沟槽。 可以将应变材料引入到沟槽中。

    Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
    10.
    发明申请
    Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow 有权
    具有应变通道区域和集成应变CMOS流的非平面pMOS结构

    公开(公告)号：US20060033095A1

    公开(公告)日：2006-02-16

    申请号：US10915780

    申请日：2004-08-10

    申请人： Brian Doyle ,  Suman Datta ,  Been-Yih Jin ,  Nancy Zelick ,  Robert Chau

    发明人： Brian Doyle ,  Suman Datta ,  Been-Yih Jin ,  Nancy Zelick ,  Robert Chau

    IPC分类号： H01L31/109

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/785 ,  H01L29/78687 ,  Y10S438/933

    摘要： A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-xGex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.

    摘要翻译： 描述了具有应变通道区域和非平面三栅极集成应变互补金属氧化物半导体（CMOS）结构的非平面三栅极p-MOS晶体管结构。 在隔离硅绝缘体（SOI）衬底上形成松弛的Si 1-x Ge层。 将轻松的Si 1-x N Ge x层图案化并随后蚀刻以在氧化物上形成翅片。 在弛豫的Si 1-x N层中Ge含量y高于Ge含量x的压应力Si 1-y Ge层， Ge层是在翅片上外延生长的。 Si 1-y Ge 3层覆盖翅片的顶部和两个侧壁。 Si 1-y Ge层中的压应力基本上增加了非平面三栅极p-MOS晶体管结构的沟道中的空穴迁移率。