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    CONTROLLING ACCESS TO STORAGE IN A COMPUTING DEVICE
    1.
    发明申请
    CONTROLLING ACCESS TO STORAGE IN A COMPUTING DEVICE 有权
    控制访问计算机设备中的存储

    公开(公告)号：US20150006871A1

    公开(公告)日：2015-01-01

    申请号：US13930643

    申请日：2013-06-28

    Applicant: Murugasamy Nachimuthu ,  Mohan Kumar ,  Dimitrios Ziakas

    Inventor： Murugasamy Nachimuthu ,  Mohan Kumar ,  Dimitrios Ziakas

    IPC: G06F12/14 ,  G06F21/57

    CPC classification number: G06F12/1408 ,  G06F21/575 ,  G06F21/78

    Abstract: In an embodiment, a computing device may include a control unit. The control unit may acquire a request from a central processing unit (CPU), contained in the computing device, that may be executing a basic input/output system (BIOS) associated with the computing device. The request may include a request for a value that may represent a maximum authorized storage size for a storage contained in the computing device. The control unit may generate the value and send the value to the CPU. The CPU may generate a system address map based on the value. The CPU may send the system address map to the control unit which may acquire the system address map and configure an address decoder, contained in the computing device, based on the acquired system address map.

    Abstract translation: 在一个实施例中，计算设备可以包括控制单元。 控制单元可以从包含在计算设备中的中央处理单元（CPU）获取可能正在执行与计算设备相关联的基本输入/输出系统（BIOS）的请求。 请求可以包括对可能表示包含在计算设备中的存储的最大授权存储大小的值的请求。 控制单元可以生成值并将值发送到CPU。 CPU可以基于该值生成系统地址映射。 CPU可以将系统地址映射发送到控制单元，控制单元可以基于所获取的系统地址映射来获取系统地址映射并且配置包含在计算设备中的地址解码器。

    Live network configuration within a link based computing system
    2.
    发明申请
    Live network configuration within a link based computing system 有权
    基于链路的计算系统中的实时网络配置

    公开(公告)号：US20070118628A1

    公开(公告)日：2007-05-24

    申请号：US11284537

    申请日：2005-11-21

    Applicant: Mohan Kumar ,  Murugasamy Nachimuthu ,  Allen Baum

    Inventor： Mohan Kumar ,  Murugasamy Nachimuthu ,  Allen Baum

    IPC: G06F15/177

    CPC classification number: H04L41/082

    Abstract: A method is described in which, in response to notice of a configuration event yet to happen within a network that is part of a link-based computing system, a component within said link based computing system: a) identifies networking configuration information changes to be made by components within the link-based computing system; and, b) sends instances of program code to each one of the components. Each instance of program code is to be executed by a specific component that it was sent to. Each instance of program code is customized to implement the particular one or more networking configuration information changes to be made at the specific component it was sent to.

    Abstract translation: 描述了一种方法，其中响应于在作为基于链路的计算系统的一部分的网络内尚未发生的配置事件的通知，所述基于链路的计算系统中的组件：a）将网络配置信息变化标识为 由基于链路的计算系统中的组件构成; 和b）将程序代码的实例发送到每个组件。 程序代码的每个实例都要由发送到的特定组件来执行。 程序代码的每个实例被定制以实现要在其发送到的特定组件上进行的特定一个或多个网络配置信息更改。

    [RSA OR HARVESTING] UNIFIED FPGA VIEW TO A COMPOSED HOST
    3.
    发明申请
    [RSA OR HARVESTING] UNIFIED FPGA VIEW TO A COMPOSED HOST 审中-公开

    公开(公告)号：US20200320033A1

    公开(公告)日：2020-10-08

    申请号：US16905395

    申请日：2020-06-18

    Applicant: Mohan Kumar ,  Murugasamy Nachimuthu

    Inventor： Mohan Kumar ,  Murugasamy Nachimuthu

    IPC: G06F13/40 ,  G06F9/455 ,  G06F15/78 ,  G06F9/50

    Abstract: Mechanisms for Field Programmable Gate Array (FPGA) chaining and unified FPGA views to a composed system hosts and associated methods, apparatus, systems and software A rack is populated with pooled system drawers including pooled compute drawers and pooled FPGA drawers communicatively coupled via input-output (IO) cables. The FPGA resources in the pooled system drawers are enumerated, identifying a location of type of each FPGA and whether it is a chainable FPGA. Intra-drawer chaining mechanisms are identified for the chainable FPGAs in each pooled compute and pooled FPGA drawer. Inter-drawer chaining mechanism are also identified for chaining FPGAs in separate pooled system drawers. The enumerated FPGA and chaining mechanism data is aggregated to generate a unified system view of the FPGA resources and their chaining mechanisms. Based on available compute nodes and FPGAs in the unified system view, new compute nodes are composed using chained FPGAs. The chained FPGAs are exposed to a hypervisor or operating system virtualization layer, or to an operating system hosted by the composed compute node as a virtual monolithic FPGA or multiple local FPGAs.

    Fault resilient boot in multi-processor systems
    4.
    发明申请
    Fault resilient boot in multi-processor systems 有权
    多处理器系统中的故障恢复启动

    公开(公告)号：US20070157011A1

    公开(公告)日：2007-07-05

    申请号：US11322997

    申请日：2005-12-30

    Applicant: Mohan Kumar ,  Murugasamy Nachimuthu

    Inventor： Mohan Kumar ,  Murugasamy Nachimuthu

    IPC: G06F15/177

    CPC classification number: G06F11/1417 ,  G06F11/0724 ,  G06F11/0757

    Abstract: In some embodiments a boot progress of a System Boot Strap Processor in a multi-processor system is monitored and a boot processor failure is detected using an Application Processor. If the boot processor failure is detected at least a portion of the system is reinitialized (and/or the system is rebooted). Other embodiments are described and claimed.

    Abstract translation: 在一些实施例中，监视多处理器系统中的系统引导带处理器的引导进程，并且使用应用处理器检测引导处理器故障。 如果检测到引导处理器故障，系统的至少一部分将被重新初始化（和/或系统重新启动）。 描述和要求保护其他实施例。

    Autonomous initialization of non-volatile random access memory in a computer system
    5.
    发明授权
    Autonomous initialization of non-volatile random access memory in a computer system 有权
    计算机系统中非易失性随机存取存储器的自动初始化

    公开(公告)号：US09378133B2

    公开(公告)日：2016-06-28

    申请号：US13997945

    申请日：2011-09-30

    Applicant: Murugasamy K. Nachimuthu ,  Mohan Kumar ,  Dimitrios Ziakas

    Inventor： Murugasamy K. Nachimuthu ,  Mohan Kumar ,  Dimitrios Ziakas

    IPC: G06F12/02 ,  G06F9/44

    CPC classification number: G06F12/0246 ,  G06F9/4403

    Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to store information that allows the NVRAM to autonomously initialize itself at power-on. The computer system includes a processor, an NVRAM controller coupled to the processor, and an NVRAM that comprises the NVRAM controller. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM stores a memory interface table containing information for the NVRAM controller to autonomously initialize the NVRAM upon power-on of the computer system without interacting with the processor and firmware outside of the NVRAM. The information is provided by the NVRAM controller to the processor to allow the processor to access the NVRAM.

    Abstract translation: 在计算机系统中使用非易失性随机存取存储器（NVRAM）来存储允许NVRAM在上电时自动初始化的信息。 计算机系统包括处理器，耦合到处理器的NVRAM控制器和包括NVRAM控制器的NVRAM。 NVRAM是字节可重写的，可由处理器字节擦除。 NVRAM存储包含NVRAM控制器的信息的存储器接口表，用于在计算机系统上电时自动初始化NVRAM，而不与NVRAM之外的处理器和固件交互。 该信息由NVRAM控制器提供给处理器，以允许处理器访问NVRAM。

    AUTONOMOUS INITIALIZATION OF NON-VOLATILE RANDOM ACCESS MEMORY IN A COMPUTER SYSTEM
    6.
    发明申请
    AUTONOMOUS INITIALIZATION OF NON-VOLATILE RANDOM ACCESS MEMORY IN A COMPUTER SYSTEM 有权
    计算机系统中非易失性随机存取存储器的自动初始化

    公开(公告)号：US20130304980A1

    公开(公告)日：2013-11-14

    申请号：US13997945

    申请日：2011-09-30

    Applicant: Murugasamy K. Nachimuthu ,  Mohan Kumar ,  Dimitrios Ziakas

    Inventor： Murugasamy K. Nachimuthu ,  Mohan Kumar ,  Dimitrios Ziakas

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F9/4403

    Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to store information that allows the NVRAM to autonomously initialize itself at power-on. The computer system includes a processor, an NVRAM controller coupled to the processor, and an NVRAM that comprises the NVRAM controller. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM stores a memory interface table containing information for the NVRAM controller to autonomously initialize the NVRAM upon power-on of the computer system without interacting with the processor and firmware outside of the NVRAM. The information is provided by the NVRAM controller to the processor to allow the processor to access the NVRAM.

    Abstract translation: 在计算机系统中使用非易失性随机存取存储器（NVRAM）来存储允许NVRAM在上电时自动初始化的信息。 计算机系统包括处理器，耦合到处理器的NVRAM控制器和包括NVRAM控制器的NVRAM。 NVRAM是字节可重写的，可由处理器字节擦除。 NVRAM存储包含NVRAM控制器的信息的存储器接口表，用于在计算机系统上电时自动初始化NVRAM，而不与NVRAM之外的处理器和固件交互。 该信息由NVRAM控制器提供给处理器，以允许处理器访问NVRAM。

    Novel substitution mutant receptors and their use in an nuclear receptor-based inducible gene expression system
    8.
    发明申请
    Novel substitution mutant receptors and their use in an nuclear receptor-based inducible gene expression system 有权
    新型取代突变体受体及其在基于核受体的诱导型基因表达系统中的应用

    公开(公告)号：US20060100416A1

    公开(公告)日：2006-05-11

    申请号：US10468193

    申请日：2002-02-20

    Applicant: Subba Palli ,  Mohan Kumar ,  Dean Cress ,  Ted Fujimoto

    Inventor： Subba Palli ,  Mohan Kumar ,  Dean Cress ,  Ted Fujimoto

    IPC: A01K67/00 ,  C07H21/04 ,  C12P21/06 ,  C07K14/715

    CPC classification number: C12N15/635 ,  C07K14/70567 ,  C07K14/721 ,  C12N7/00 ,  C12N15/86 ,  C12N2710/10043 ,  C12P21/02

    Abstract: This invention relates to the field of biotechnology or genetic engineering. Specifically, this invention relates to the field of gene expression. More specifically, this invention relates to novel substitution mutant receptors and their use in a Group H nuclear receptor-based inducible gene expression system and methods of modulating the expression of a gene in a host cell for applications such as gene therapy, large scale production of proteins and antibodies, cell-based high throughput screening assays, functional genomics and regulation of traits in transgenic organisms.

    Abstract translation: 本发明涉及生物技术或遗传工程领域。 具体地，本发明涉及基因表达领域。 更具体地，本发明涉及新的取代突变体受体及其在基于H核受体的诱导型基因表达系统中的用途以及调节宿主细胞中基因表达的方法，用于基因治疗，大规模生产 蛋白质和抗体，基于细胞的高通量筛选测定，功能基因组学和转基因生物体中性状的调节。

    Network-based system and method for global roaming
    9.
    发明申请
    Network-based system and method for global roaming 有权
    基于网络的全球漫游系统和方法

    公开(公告)号：US20050192007A1

    公开(公告)日：2005-09-01

    申请号：US11061750

    申请日：2005-02-18

    Applicant: G.V. Kumar ,  Harish Amilineni ,  Mohan Kumar ,  Prakash Senapati

    Inventor： G.V. Kumar ,  Harish Amilineni ,  Mohan Kumar ,  Prakash Senapati

    IPC: H04W8/06 ,  H04W8/12 ,  H04M11/00 ,  H04M1/66 ,  H04M1/68

    CPC classification number: H04W8/04 ,  H04W4/90 ,  H04W8/06 ,  H04W8/12

    Abstract: A system and method of mobile communication roaming where a subscriber's home network and a roaming network used by the subscriber do not have a roaming agreement. The roaming network sends a “Send Authentication/Parameters” request to the home network via an intelligent roaming system on or attached to the backbone. The home network sends an authentication response to the “Send Authentication/Parameters” request from the home network to the roaming network via the backbone and intelligent roaming system. The roaming network sends a “Update Location” request from the roaming network to the intelligent roaming system. The visitor locator register (VLR) address in the “Update Location” request is replaced with the VLR address of the intelligent roaming system to create a modified update request. The modified update request is sent from the intelligent roaming system to the home network. The home network sends an update response to the modified update request to the roaming network via the backbone and intelligent roaming system.

    Abstract translation: 移动通信漫游的系统和方法，其中订户的家庭网络和用户使用的漫游网络不具有漫游协议。 漫游网络通过智能漫游系统向主网络发送“发送认证/参数”请求，该智能漫游系统在骨干网上或连接到骨干网。 家庭网络通过骨干网和智能漫游系统向家庭网络向漫游网络发送“发送认证/参数”请求的认证响应。 漫游网络从漫游网络向智能漫游系统发送“更新位置”请求。 “更新位置”请求中的访问者定位器寄存器（VLR）地址被智能漫游系统的VLR地址替换，以创建修改的更新请求。 修改的更新请求从智能漫游系统发送到家庭网络。 家庭网络通过骨干网和智能漫游系统向漫游网络发送对修改的更新请求的更新响应。

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