Abstract:
In an embodiment, a computing device may include a control unit. The control unit may acquire a request from a central processing unit (CPU), contained in the computing device, that may be executing a basic input/output system (BIOS) associated with the computing device. The request may include a request for a value that may represent a maximum authorized storage size for a storage contained in the computing device. The control unit may generate the value and send the value to the CPU. The CPU may generate a system address map based on the value. The CPU may send the system address map to the control unit which may acquire the system address map and configure an address decoder, contained in the computing device, based on the acquired system address map.
Abstract:
A method is described in which, in response to notice of a configuration event yet to happen within a network that is part of a link-based computing system, a component within said link based computing system: a) identifies networking configuration information changes to be made by components within the link-based computing system; and, b) sends instances of program code to each one of the components. Each instance of program code is to be executed by a specific component that it was sent to. Each instance of program code is customized to implement the particular one or more networking configuration information changes to be made at the specific component it was sent to.
Abstract:
Mechanisms for Field Programmable Gate Array (FPGA) chaining and unified FPGA views to a composed system hosts and associated methods, apparatus, systems and software A rack is populated with pooled system drawers including pooled compute drawers and pooled FPGA drawers communicatively coupled via input-output (IO) cables. The FPGA resources in the pooled system drawers are enumerated, identifying a location of type of each FPGA and whether it is a chainable FPGA. Intra-drawer chaining mechanisms are identified for the chainable FPGAs in each pooled compute and pooled FPGA drawer. Inter-drawer chaining mechanism are also identified for chaining FPGAs in separate pooled system drawers. The enumerated FPGA and chaining mechanism data is aggregated to generate a unified system view of the FPGA resources and their chaining mechanisms. Based on available compute nodes and FPGAs in the unified system view, new compute nodes are composed using chained FPGAs. The chained FPGAs are exposed to a hypervisor or operating system virtualization layer, or to an operating system hosted by the composed compute node as a virtual monolithic FPGA or multiple local FPGAs.
Abstract:
In some embodiments a boot progress of a System Boot Strap Processor in a multi-processor system is monitored and a boot processor failure is detected using an Application Processor. If the boot processor failure is detected at least a portion of the system is reinitialized (and/or the system is rebooted). Other embodiments are described and claimed.
Abstract:
A non-volatile random access memory (NVRAM) is used in a computer system to store information that allows the NVRAM to autonomously initialize itself at power-on. The computer system includes a processor, an NVRAM controller coupled to the processor, and an NVRAM that comprises the NVRAM controller. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM stores a memory interface table containing information for the NVRAM controller to autonomously initialize the NVRAM upon power-on of the computer system without interacting with the processor and firmware outside of the NVRAM. The information is provided by the NVRAM controller to the processor to allow the processor to access the NVRAM.
Abstract:
A non-volatile random access memory (NVRAM) is used in a computer system to store information that allows the NVRAM to autonomously initialize itself at power-on. The computer system includes a processor, an NVRAM controller coupled to the processor, and an NVRAM that comprises the NVRAM controller. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM stores a memory interface table containing information for the NVRAM controller to autonomously initialize the NVRAM upon power-on of the computer system without interacting with the processor and firmware outside of the NVRAM. The information is provided by the NVRAM controller to the processor to allow the processor to access the NVRAM.
Abstract:
A system and method of real-time interconnect billing to facilitate invoicing and reconciliation between interconnected communication and service providers. The fully customizable, scalable, and network-based system rates and monitors costs, incorporates agreements between interconnected providers, invoices, bills, and reconciles to establish an accurate and cost-effective accounting of provider revenues and costs. The system is able to communicate with devices, networks, and interconnect providers to obtain, provide and exchange billing information and payments. The system updates subscriber accounts and alerts the home provider, subscribers, interconnect providers and users of these updates.
Abstract:
This invention relates to the field of biotechnology or genetic engineering. Specifically, this invention relates to the field of gene expression. More specifically, this invention relates to novel substitution mutant receptors and their use in a Group H nuclear receptor-based inducible gene expression system and methods of modulating the expression of a gene in a host cell for applications such as gene therapy, large scale production of proteins and antibodies, cell-based high throughput screening assays, functional genomics and regulation of traits in transgenic organisms.
Abstract:
A system and method of mobile communication roaming where a subscriber's home network and a roaming network used by the subscriber do not have a roaming agreement. The roaming network sends a “Send Authentication/Parameters” request to the home network via an intelligent roaming system on or attached to the backbone. The home network sends an authentication response to the “Send Authentication/Parameters” request from the home network to the roaming network via the backbone and intelligent roaming system. The roaming network sends a “Update Location” request from the roaming network to the intelligent roaming system. The visitor locator register (VLR) address in the “Update Location” request is replaced with the VLR address of the intelligent roaming system to create a modified update request. The modified update request is sent from the intelligent roaming system to the home network. The home network sends an update response to the modified update request to the roaming network via the backbone and intelligent roaming system.
Abstract:
A system and method of real-time interconnect billing to facilitate invoicing and reconciliation between interconnected communication and service providers. The fully customizable, scalable, and network-based system rates and monitors costs, incorporates agreements between interconnected providers, invoices, bills, and reconciles to establish an accurate and cost-effective accounting of provider revenues and costs. The system is able to communicate with devices, networks, and interconnect providers to obtain, provide and exchange billing information and payments. The system updates subscriber accounts and alerts the home provider, subscribers, interconnect providers and users of these updates.