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公开(公告)号：US20070118628A1
公开(公告)日：2007-05-24
申请号：US11284537
申请日：2005-11-21
申请人： Mohan Kumar , Murugasamy Nachimuthu , Allen Baum
发明人： Mohan Kumar , Murugasamy Nachimuthu , Allen Baum
IPC分类号： G06F15/177
CPC分类号： H04L41/082
摘要： A method is described in which, in response to notice of a configuration event yet to happen within a network that is part of a link-based computing system, a component within said link based computing system: a) identifies networking configuration information changes to be made by components within the link-based computing system; and, b) sends instances of program code to each one of the components. Each instance of program code is to be executed by a specific component that it was sent to. Each instance of program code is customized to implement the particular one or more networking configuration information changes to be made at the specific component it was sent to.
摘要翻译： 描述了一种方法，其中响应于在作为基于链路的计算系统的一部分的网络内尚未发生的配置事件的通知，所述基于链路的计算系统中的组件：a）将网络配置信息变化标识为 由基于链路的计算系统中的组件构成; 和b）将程序代码的实例发送到每个组件。 程序代码的每个实例都要由发送到的特定组件来执行。 程序代码的每个实例被定制以实现要在其发送到的特定组件上进行的特定一个或多个网络配置信息更改。
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公开(公告)号：US08145732B2
公开(公告)日：2012-03-27
申请号：US11284537
申请日：2005-11-21
IPC分类号： G06F15/177 , G06F15/173 , G06F15/16 , G06F11/00 , G06F9/44 , G06F9/445 , H04L12/28 , H04B1/38 , G06Q10/00 , G06Q30/00
CPC分类号： H04L41/082
摘要： A method is described in which, in response to notice of a configuration event yet to happen within a network that is part of a link-based computing system, a component within said link based computing system: a) identifies networking configuration information changes to be made by components within the link-based computing system; and, b) sends instances of program code to each one of the components. Each instance of program code is to be executed by a specific component that it was sent to. Each instance of program code is customized to implement the particular one or more networking configuration information changes to be made at the specific component it was sent to.
摘要翻译： 描述了一种方法，其中响应于在作为基于链路的计算系统的一部分的网络内尚未发生的配置事件的通知，所述基于链路的计算系统中的组件：a）将网络配置信息变化标识为 由基于链路的计算系统中的组件构成; 和b）将程序代码的实例发送到每个组件。 程序代码的每个实例都要由发送到的特定组件来执行。 程序代码的每个实例被定制以实现要在其发送到的特定组件上进行的特定一个或多个网络配置信息更改。
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3.发明授权Method and apparatus for communication between two or more processing elements 失效用于在两个或多个处理元件之间进行通信的方法和装置公开(公告)号：US08645959B2
公开(公告)日：2014-02-04
申请号：US11095341
申请日：2005-03-30
申请人： Kushagra Vaid , John Crawford , Allen Baum
发明人： Kushagra Vaid , John Crawford , Allen Baum
IPC分类号： G06F9/46
摘要： A technique for performing barrier synchronization among a plurality of program threads. More particularly, at least one embodiment of the invention keeps track of completed tasks associated with a number of program threads using bits within a barrier register that can be updated and reassigned without incurring the amount of bus traffic as in the prior art.
摘要翻译： 一种用于在多个程序线程之间执行屏障同步的技术。 更具体地，本发明的至少一个实施例使用可以被更新和重新分配的屏障寄存器内的位来跟踪与多个程序线程相关联的完成的任务，而不会像现有技术那样产生总线流量。
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公开(公告)号：US07804890B2
公开(公告)日：2010-09-28
申请号：US11166030
申请日：2005-06-23
申请人： Muraleedhara H. Navada , Tim Frodsham , Sanjay Dabral , Allen Baum , Chris D. Matthews , Chris C. Gianos , Rahul R. Shah , Theodore Z. Schoenborn
发明人： Muraleedhara H. Navada , Tim Frodsham , Sanjay Dabral , Allen Baum , Chris D. Matthews , Chris C. Gianos , Rahul R. Shah , Theodore Z. Schoenborn
IPC分类号： H04B3/46
CPC分类号： H04L7/10 , H04L7/0008 , H04L7/0041
摘要： A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.
摘要翻译： 关于改进对测试矢量的集成设备确定性响应的讨论。 例如，通过将初始化训练序列同步到复位失效来限制在已知边界内的集成设备的响应的传输延迟。 具体地，该提议通过使训练序列同步并随后将颤振传输同步到由参考时钟采样的复位断言来促进来自DUT的响应确定性。
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公开(公告)号：US20060174182A1
公开(公告)日：2006-08-03
申请号：US11046491
申请日：2005-01-28
申请人： Henk Neefs , Allen Baum
发明人： Henk Neefs , Allen Baum
IPC分类号： H03M13/00
CPC分类号： H03M13/3746 , H03M13/09 , H03M13/098
摘要： An embodiment of the present invention is a technique to perform error correction using a trial-and-error method. A syndrome generator provides a generation of a data syndrome of a data word modified according to a selection of at least one of error correcting parameters. The data word is associated with at least one transaction performed on a unit. A controller controls iterating the generation of the data syndrome.
摘要翻译： 本发明的实施例是使用试错法进行纠错的技术。 校正子发生器提供根据至少一个纠错参数的选择修改的数据字的数据校正子的产生。 数据字与在一个单元上执行的至少一个事务相关联。 控制器控制迭代数据综合征的产生。
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公开(公告)号：US20070150699A1
公开(公告)日：2007-06-28
申请号：US11321213
申请日：2005-12-28
申请人： Ioannis Schoinas , Doddaballapur Jayasimha , Eric Delano , Allen Baum , Akhilesh Kumar , Steven Chang , Suresh Chittor , Kenneth Creta , Stephen Van Doren
发明人： Ioannis Schoinas , Doddaballapur Jayasimha , Eric Delano , Allen Baum , Akhilesh Kumar , Steven Chang , Suresh Chittor , Kenneth Creta , Stephen Van Doren
IPC分类号： G06F15/00
摘要： Methods and apparatuses for firm partitioning of a computing platform.
摘要翻译： 用于计算平台的固定分区的方法和装置。
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公开(公告)号：US20050259696A1
公开(公告)日：2005-11-24
申请号：US10850809
申请日：2004-05-21
申请人： Maurice Steinman , Rahul Shah , Naveen Cherukuri , Aaron Spink , Allen Baum , Sanjay Dabral , Tim Frodsham , David Dunning , Theodore Schoenborn
发明人： Maurice Steinman , Rahul Shah , Naveen Cherukuri , Aaron Spink , Allen Baum , Sanjay Dabral , Tim Frodsham , David Dunning , Theodore Schoenborn
CPC分类号： G06F13/4018 , G06F13/4009 , Y02D10/14 , Y02D10/151
摘要： Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.
摘要翻译： 本发明的实施例提供了一种用于将链路划分成一个或多个缩小宽度链路的算法。 对于本发明的一个实施例，采用复用方案来实现特定循环冗余校验所需的位传输顺序。 多路复用的输出位随后在芯片上转动，以减少车载路由拥塞。
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公开(公告)号：US4928239A
公开(公告)日：1990-05-22
申请号：US358460
申请日：1989-05-26
CPC分类号： G06F9/3824 , G06F12/0862 , G06F12/127 , G06F12/126 , G06F2212/6028
摘要： An instruction is presented to the cache; the instruction includes a cache control specifier which identifies a type of data being requested. Based on the cache control specifier, one of a plurality of replacement schemes is selected for swapping a data block out of the cache.
摘要翻译： 向缓存提供指令; 该指令包括一个高速缓存控制说明符，用于标识被请求的数据类型。 基于高速缓存控制说明符，选择多个替换方案之一用于将高速缓存中的数据块交换。
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9.发明授权Privilege level checking instruction for implementing a secure hierarchical computer system 失效用于实施安全分级计算机系统的权限级别检查指令
公开(公告)号：US4809160A
公开(公告)日：1989-02-28
申请号：US792702
申请日：1985-10-28
CPC分类号： G06F9/468 , G06F9/45537
摘要： A low overhead way for insuring that only routines of sufficient privilege can execute on a secured page of memory in an hierarchial computer system, and for raising the privilege level of a low privilege process in an orderly and secure way is presented. This is done through the execution of a single "gateway" branch instruction standing between a procedure call by a lower privileged routine, such as a user program, and an operating system itself.
摘要翻译： 提供了一种低开销方式，用于确保仅有足够权限的例程可以在分层计算机系统中的存储器的安全页面上执行，并且以有序和安全的方式提高低特权过程的特权级别。 这通过执行站在诸如用户程序的较低特权例程的过程调用与操作系统本身之间的单个“网关”分支指令来完成。
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公开(公告)号：US4713755A
公开(公告)日：1987-12-15
申请号：US750381
申请日：1985-06-28
CPC分类号： G06F9/3812 , G06F12/0804 , G06F12/0837 , Y10S707/99934
摘要： Memory integrity is maintained in a system with a hierarchical memory using a set of explicit cache control instructions. The caches in the system have two status flags, a valid bit and a dirty bit, with each block of information stored. The operating system executes selected cache control instructions to ensure memory integrity whenever there is a possibility that integrity could be compromised.
摘要翻译： 在使用一组显式高速缓存控制指令的分层存储器的系统中维持存储器完整性。 系统中的缓存具有两个状态标志，一个有效位和一个脏位，每个信息块都被存储。 操作系统执行选定的缓存控制指令，以确保内存完整性，只要可能会危及完整性。
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