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    Memory device
    2.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US08723297B2

    公开(公告)日：2014-05-13

    申请号：US13177984

    申请日：2011-07-07

    申请人： Yoon-Ho Son ,  Mong-Sup Lee ,  In-Seak Hwang ,  Dae-Hyuk Chung ,  Suk-Hun Choi ,  Sang-Jun Lee

    发明人： Yoon-Ho Son ,  Mong-Sup Lee ,  In-Seak Hwang ,  Dae-Hyuk Chung ,  Suk-Hun Choi ,  Sang-Jun Lee

    IPC分类号： H01L27/115

    CPC分类号： H01L27/10888 ,  H01L21/02057 ,  H01L21/02063 ,  H01L21/30608 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10814 ,  H01L27/10855 ,  H01L29/1037 ,  H01L29/41766 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced.

    摘要翻译： 在具有接触结构和衬底之间的扩大的接触面积的半导体器件中，衬底可以包括布置有导电结构的第一区域和限定第一区域的第二区域。 第一区域可以包括多面多面体凹部，其中至少一个侧壁相对于基底的表面倾斜。 可以在衬底上形成足够覆盖导电结构的厚度的绝缘层。 绝缘层具有可与凹部连通的接触孔。 基板的有源区域通过接触孔露出。 导电图案位于凹槽和接触孔中。 因此，即使图案线的间隙距离和线宽减小，也可以将基板的有源区域的接触电阻保持在较低的值。

    MEMORY DEVICE
    3.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20120025283A1

    公开(公告)日：2012-02-02

    申请号：US13177984

    申请日：2011-07-07

    申请人： Yoon-Ho Son ,  Mong-Sup Lee ,  In-Seak Hwang ,  Dae-Hyuk Chung ,  Suk-Hun Choi ,  Sang-Jun Lee

    发明人： Yoon-Ho Son ,  Mong-Sup Lee ,  In-Seak Hwang ,  Dae-Hyuk Chung ,  Suk-Hun Choi ,  Sang-Jun Lee

    IPC分类号： H01L27/108 ,  H01L29/06

    CPC分类号： H01L27/10888 ,  H01L21/02057 ,  H01L21/02063 ,  H01L21/30608 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10814 ,  H01L27/10855 ,  H01L29/1037 ,  H01L29/41766 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced.

    摘要翻译： 在具有接触结构和衬底之间的扩大的接触面积的半导体器件中，衬底可以包括布置有导电结构的第一区域和限定第一区域的第二区域。 第一区域可以包括多面多面体凹部，其中至少一个侧壁相对于基底的表面倾斜。 可以在衬底上形成足够覆盖导电结构的厚度的绝缘层。 绝缘层具有可与凹部连通的接触孔。 基板的有源区域通过接触孔露出。 导电图案位于凹槽和接触孔中。 因此，即使图案线的间隙距离和线宽减小，也可以将基板的有源区域的接触电阻保持在较低的值。

    Methods of fabricating a semiconductor device
    5.
    发明申请
    Methods of fabricating a semiconductor device 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20070254425A1

    公开(公告)日：2007-11-01

    申请号：US11654543

    申请日：2007-01-18

    申请人： Sang-Yong Kim ,  Mong-Sup Lee ,  Chang-Ki Hong ,  Woo-Gwan Shim

    发明人： Sang-Yong Kim ,  Mong-Sup Lee ,  Chang-Ki Hong ,  Woo-Gwan Shim

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/1052

    摘要： Example embodiments of the present invention relates to methods of fabricating a semiconductor device. Other example embodiments of the present invention relate to methods of fabricating a semiconductor device using a metal nitride layer as a gate electrode. The methods may include providing a semiconductor substrate having a first region and a second region. A gate insulating layer, a metal nitride layer and/or an amorphous carbon layer may be sequentially formed on the substrate. The amorphous carbon layer may be selectively etched, forming an amorphous carbon mask covering the first region. The metal nitride layer, exposed by the amorphous carbon mask, may be etched, forming a preliminary metal nitride pattern. The amorphous carbon mask may be removed.

    摘要翻译： 本发明的示例性实施例涉及制造半导体器件的方法。 本发明的其他示例性实施例涉及使用金属氮化物层作为栅电极制造半导体器件的方法。 所述方法可以包括提供具有第一区域和第二区域的半导体衬底。 可以在衬底上依次形成栅极绝缘层，金属氮化物层和/或非晶碳层。 可以选择性地蚀刻无定形碳层，形成覆盖第一区域的无定形碳掩模。 可以蚀刻由非晶碳掩模曝光的金属氮化物层，形成初步的金属氮化物图案。 可以除去无定形碳掩模。