公开(公告)号：US20080188049A1

公开(公告)日：2008-08-07

申请号：US12022735

申请日：2008-01-30

申请人： Woo Gwan Shim ,  Mong-Sup Lee ,  Ji-Hoon Cha ,  Chang-Ki Hong ,  Kun-Tack Lee

发明人： Woo Gwan Shim ,  Mong-Sup Lee ,  Ji-Hoon Cha ,  Chang-Ki Hong ,  Kun-Tack Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/513

摘要： Methods of manufacturing non-volatile memory devices are provided including sequentially forming a tunnel insulating layer, a charge-trapping layer, a blocking layer and a conductive layer on a substrate having a channel region. The conductive layer is patterned to form a word line structure, and the blocking layer and the charge-trapping layer are etched using an aqueous acid solution as an etching solution to form a blocking layer pattern and a charge-trapping layer pattern.

摘要翻译： 提供制造非易失性存储器件的方法包括在具有沟道区的衬底上顺序地形成隧道绝缘层，电荷俘获层，阻挡层和导电层。 图案化导电层以形成字线结构，并且使用酸性水溶液作为蚀刻溶液来蚀刻阻挡层和电荷俘获层，以形成阻挡层图案和电荷俘获层图案。

公开(公告)号：US20070254425A1

公开(公告)日：2007-11-01

申请号：US11654543

申请日：2007-01-18

申请人： Sang-Yong Kim ,  Mong-Sup Lee ,  Chang-Ki Hong ,  Woo-Gwan Shim

发明人： Sang-Yong Kim ,  Mong-Sup Lee ,  Chang-Ki Hong ,  Woo-Gwan Shim

IPC分类号： H01L21/8238

CPC分类号： H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/1052

摘要： Example embodiments of the present invention relates to methods of fabricating a semiconductor device. Other example embodiments of the present invention relate to methods of fabricating a semiconductor device using a metal nitride layer as a gate electrode. The methods may include providing a semiconductor substrate having a first region and a second region. A gate insulating layer, a metal nitride layer and/or an amorphous carbon layer may be sequentially formed on the substrate. The amorphous carbon layer may be selectively etched, forming an amorphous carbon mask covering the first region. The metal nitride layer, exposed by the amorphous carbon mask, may be etched, forming a preliminary metal nitride pattern. The amorphous carbon mask may be removed.

摘要翻译： 本发明的示例性实施例涉及制造半导体器件的方法。 本发明的其他示例性实施例涉及使用金属氮化物层作为栅电极制造半导体器件的方法。 所述方法可以包括提供具有第一区域和第二区域的半导体衬底。 可以在衬底上依次形成栅极绝缘层，金属氮化物层和/或非晶碳层。 可以选择性地蚀刻无定形碳层，形成覆盖第一区域的无定形碳掩模。 可以蚀刻由非晶碳掩模曝光的金属氮化物层，形成初步的金属氮化物图案。 可以除去无定形碳掩模。

公开(公告)号：US20100173470A1

公开(公告)日：2010-07-08

申请号：US12654933

申请日：2010-01-08

申请人： Mong-Sup Lee ,  In-Seak Hwang ,  Keum-Joo Lee ,  Jin-Hye Bae ,  Bo-Wo Choi ,  Seung-Jae Lee

发明人： Mong-Sup Lee ,  In-Seak Hwang ,  Keum-Joo Lee ,  Jin-Hye Bae ,  Bo-Wo Choi ,  Seung-Jae Lee

IPC分类号： H01L21/762 ,  H01L21/3105

CPC分类号： H01L21/3125 ,  C08G77/62 ,  C09D183/02 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/316 ,  H01L21/76229

摘要： In a method of forming a silicon oxide layer, a spin-on-glass (SOG) layer may be formed on an object including a recess using an SOG composition. The SOG layer may be pre-baked and then cured by contacting with at least one material selected from the group consisting of water, a basic material and an oxidant, under a pressure of from about 1.5 atm to about 100 atm. The cured SOG layer may be baked.

摘要翻译： 在形成氧化硅层的方法中，可以使用SOG组合物在包括凹部的物体上形成旋涂玻璃（SOG）层。 可以在约1.5atm至约100atm的压力下，预先将SOG层与至少一种选自水，碱性物质和氧化剂的材料接触固化，然后固化。 固化的SOG层可以被烘烤。

公开(公告)号：US08723297B2

公开(公告)日：2014-05-13

申请号：US13177984

申请日：2011-07-07

申请人： Yoon-Ho Son ,  Mong-Sup Lee ,  In-Seak Hwang ,  Dae-Hyuk Chung ,  Suk-Hun Choi ,  Sang-Jun Lee

发明人： Yoon-Ho Son ,  Mong-Sup Lee ,  In-Seak Hwang ,  Dae-Hyuk Chung ,  Suk-Hun Choi ,  Sang-Jun Lee

IPC分类号： H01L27/115

CPC分类号： H01L27/10888 ,  H01L21/02057 ,  H01L21/02063 ,  H01L21/30608 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10814 ,  H01L27/10855 ,  H01L29/1037 ,  H01L29/41766 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced.

摘要翻译： 在具有接触结构和衬底之间的扩大的接触面积的半导体器件中，衬底可以包括布置有导电结构的第一区域和限定第一区域的第二区域。 第一区域可以包括多面多面体凹部，其中至少一个侧壁相对于基底的表面倾斜。 可以在衬底上形成足够覆盖导电结构的厚度的绝缘层。 绝缘层具有可与凹部连通的接触孔。 基板的有源区域通过接触孔露出。 导电图案位于凹槽和接触孔中。 因此，即使图案线的间隙距离和线宽减小，也可以将基板的有源区域的接触电阻保持在较低的值。

公开(公告)号：US20120025283A1

公开(公告)日：2012-02-02

申请号：US13177984

申请日：2011-07-07

申请人： Yoon-Ho Son ,  Mong-Sup Lee ,  In-Seak Hwang ,  Dae-Hyuk Chung ,  Suk-Hun Choi ,  Sang-Jun Lee

发明人： Yoon-Ho Son ,  Mong-Sup Lee ,  In-Seak Hwang ,  Dae-Hyuk Chung ,  Suk-Hun Choi ,  Sang-Jun Lee

IPC分类号： H01L27/108 ,  H01L29/06

CPC分类号： H01L27/10888 ,  H01L21/02057 ,  H01L21/02063 ,  H01L21/30608 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10814 ,  H01L27/10855 ,  H01L29/1037 ,  H01L29/41766 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced.

摘要翻译： 在具有接触结构和衬底之间的扩大的接触面积的半导体器件中，衬底可以包括布置有导电结构的第一区域和限定第一区域的第二区域。 第一区域可以包括多面多面体凹部，其中至少一个侧壁相对于基底的表面倾斜。 可以在衬底上形成足够覆盖导电结构的厚度的绝缘层。 绝缘层具有可与凹部连通的接触孔。 基板的有源区域通过接触孔露出。 导电图案位于凹槽和接触孔中。 因此，即使图案线的间隙距离和线宽减小，也可以将基板的有源区域的接触电阻保持在较低的值。