利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

89 条记录 (耗时 0.035 秒)

    Memory having ferroelectric capacitors polarized in nonvolatile mode
    1.
    发明授权
    Memory having ferroelectric capacitors polarized in nonvolatile mode 失效
    具有以非易失性模式极化的铁电电容器的存储器

    公开(公告)号：US5297077A

    公开(公告)日：1994-03-22

    申请号：US676546

    申请日：1991-03-28

    申请人： Motomasa Imai ,  Hiroshi Toyoda ,  Kazuhide Abe ,  Koji Yamakawa ,  Hisakazu Iizuka ,  Mitsuo Harata ,  Koji Sakui

    发明人： Motomasa Imai ,  Hiroshi Toyoda ,  Kazuhide Abe ,  Koji Yamakawa ,  Hisakazu Iizuka ,  Mitsuo Harata ,  Koji Sakui

    IPC分类号： G11C11/22 ,  G11C14/00

    CPC分类号： G11C14/00 ,  G11C11/22

    摘要： A semiconductor memory device comprises a ferroelectric capacitor, a voltage output circuit for outputting a first voltage for reversely polarizing the ferroelectric capacitor and a second voltage by which the polarization of the ferroelectric capacitor is not reversed, regardless of data stored in the ferroelectric capacitor, a first reference capacitor having a such a capacitance as to accumulate less charge than charge which the ferroelectric capacitor accumulates, when the second voltage is applied to the ferroelectric capacitor, a second reference capacitor having such a capacitance that as to accumulate greater charge than the charge which the ferroelectric capacitor accumulates while the ferroelectric capacitor is forwardly polarized, when the first voltage is applied to the ferroelectric capacitor, thus reversely polarizing the ferroelectric capacitor, a sense amplifier connected to the ferroelectric capacitor and the first or second reference capacitor, a reference-capacitor selecting circuit for connecting the first reference capacitor to the sense amplifier when the voltage output circuit outputs the second voltage, and connecting the second reference capacitor to the sense amplifier while the voltage output circuit outputs the first voltage, and a circuit for determining data from the presence or absence of an electric charge in the ferroelectric capacitors while the memory is set in volatile mode, and for determining data from the direction in which the ferroelectric capacitor is polarized, while the memory is set in nonvolatile mode.

    摘要翻译： 半导体存储器件包括铁电电容器，用于输出用于使强电介质电容器反向极化的第一电压的电压输出电路和强电介质电容器的极化不反转的第二电压，而与铁电电容器中存储的数据无关 第一参考电容器具有这样的电容，即当第二电压被施加到铁电电容器时，积累比铁电电容器累积的电荷少的电荷，第二参考电容器具有这样的电容，以便积累比电荷更大的电荷 当铁电电容器向前偏振时，铁电电容器累积，当第一电压施加到铁电电容器时，从而使铁电电容器反向极化，连接到铁电电容器和第一或第二参考电容器的读出放大器，参考电容器 s 选择电路，用于当电压输出电路输出第二电压时将第一参考电容器连接到读出放大器，并且在电压输出电路输出第一电压时将第二参考电容器连接到读出放大器;以及电路，用于从 当存储器被设置为易失性模式时，铁电电容器中存在或不存在电荷，并且用于从存储器设置为非易失性模式时从铁电电容器被极化的方向确定数据。

    Non-volatile semiconductor memory device capable of electrically performing read and write operation and method of reading information from the same
    3.
    发明授权
    Non-volatile semiconductor memory device capable of electrically performing read and write operation and method of reading information from the same 失效
    能够电性地执行读写操作的非挥发性半导体存储器件和从其读取信息的方法

    公开(公告)号：US5517445A

    公开(公告)日：1996-05-14

    申请号：US784073

    申请日：1991-10-30

    申请人： Motomasa Imai ,  Kazuhide Abe ,  Koji Yamakawa ,  Hiroshi Toyoda ,  Yoshiko Kohanawa ,  Mitsuo Harata

    发明人： Motomasa Imai ,  Kazuhide Abe ,  Koji Yamakawa ,  Hiroshi Toyoda ,  Yoshiko Kohanawa ,  Mitsuo Harata

    IPC分类号： G11C11/22 ,  G11C17/04

    CPC分类号： G11C11/22

    摘要： A non-volatile semiconductor memory device, includes a memory cell having a capacitor formed by stacking a semiconductor layer and a ferroelectric layer between a pair of electrodes, the semiconductor layer and the ferroelectric layer forming a semiconductor-ferroelectric junction, a writing circuit in which a voltage higher than a coercive electric field of the ferroelectric material is applied to the capacitor of the memory cell to align a polarization direction of the ferroelectric layer in a predetermined direction so as to set a capacitance of the capacitor at a predetermined value, thereby writing data corresponding to the predetermined value of the capacitance, and a reading circuit in which a voltage less than the coercive electric field of the ferroelectric layer is applied to the capacitor of the memory cell in which the data is written, thereby reading the data.

    摘要翻译： 一种非易失性半导体存储器件，包括具有电容器的存储单元，所述电容器通过在一对电极之间堆叠半导体层和铁电层而形成，所述半导体层和形成半导体 - 铁电结的铁电层，其中写入电路 将高于铁电材料的矫顽电场的电压施加到存储单元的电容器，以将铁电层的偏振方向沿预定方向对齐，以将电容器的电容设置在预定值，从而写入 对应于电容的预定值的数据，以及读取电路，其中将低于铁电层的矫顽电场的电压施加到其中写入数据的存储单元的电容器，从而读取数据。

    Semiconductor memory device using ferroelectric capacitor and having only one sense amplifier selected
    4.
    发明授权
    Semiconductor memory device using ferroelectric capacitor and having only one sense amplifier selected 失效
    使用铁电电容器并且仅选择一个读出放大器的半导体存储器件

    公开(公告)号：US5400275A

    公开(公告)日：1995-03-21

    申请号：US712092

    申请日：1991-06-07

    申请人： Kazuhide Abe ,  Hiroshi Toyoda ,  Koji Yamakawa ,  Motomasa Imai ,  Koji Sakui

    发明人： Kazuhide Abe ,  Hiroshi Toyoda ,  Koji Yamakawa ,  Motomasa Imai ,  Koji Sakui

    IPC分类号： G11C11/22 ,  H01L27/115 ,  G11C7/00

    CPC分类号： H01L27/11502 ,  G11C11/22

    摘要： A semiconductor memory device comprises a plurality of memory cells arranged in the form of a matrix to constitute rows-and columns, a plurality of first driving lines, connected to the memory cells, for transmitting a first driving signal to the memory cells, one of the plurality of first driving lines being selected by a row address, a plurality of second driving lines, connected to the memory cells, for transmitting a second driving signal to the memory cells, one of the plurality of second driving lines being selected by a column address, a plurality of read/write lines, connected to the memory cells, for performing read/write operations with respect to the memory cells, and a plurality of sense amplifiers connected to the read/ write lines, wherein one of the plurality of sense amplifiers is selected by the column address, and the memory cells in the same column are connected to the same sense amplifier through the read/write lines.

    摘要翻译： 一种半导体存储器件包括以矩阵形式布置以构成行和列的多个存储器单元，连接到存储器单元的多条第一驱动线，用于将第一驱动信号发送到存储器单元，其中之一 所述多个第一驱动线由行地址选择，多个第二驱动线连接到所述存储单元，用于将第二驱动信号发送到所述存储单元，所述多个第二驱动线中的一个由列选择 连接到存储器单元的多个读/写线，用于对存储单元执行读/写操作，以及连接到读/写线的多个读出放大器，其中多个感测中的一个 放大器由列地址选择，同一列中的存储单元通过读/写线连接到相同的读出放大器。