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    Thin film transistor substrate and display device
    1.
    发明授权
    Thin film transistor substrate and display device 有权
    薄膜晶体管基板和显示装置

    公开(公告)号：US08217397B2

    公开(公告)日：2012-07-10

    申请号：US12812913

    申请日：2009-01-15

    申请人： Mototaka Ochi ,  Nobuyuki Kawakami ,  Katsufumi Tomihisa ,  Hiroshi Goto

    发明人： Mototaka Ochi ,  Nobuyuki Kawakami ,  Katsufumi Tomihisa ,  Hiroshi Goto

    IPC分类号： H01L27/14 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036

    CPC分类号： H01L29/458

    摘要： The present invention provides a thin film transistor substrate and a display device in which a decrease in the dry etching rate of a source electrode and drain electrode is not caused; no etching residues are generated; and a barrier metal can be eliminated between a semiconductor layer and metal wires such as the source and drain electrodes. The present invention is a thin film transistor substrate having a semiconductor layer 1, a source electrode 2, a drain electrode 3, and a transparent conductive film 4, in which the source electrode 2 and drain electrode 3 are formed by patterning by means of dry etching and comprises an Al alloy thin film comprising 0.1 to 1.5 atom % of Si and/or Ge, 0.1 to 3.0 atom % of Ni and/or Co, and 0.1 to 0.5 atom % of La and/or Nd, and the thin film transistor is directly connected with the semiconductor layer 1.

    摘要翻译： 本发明提供一种薄膜晶体管基板和显示装置，其中不会引起源电极和漏电极的干蚀刻速率的降低; 不产生蚀刻残留物; 并且可以在半导体层和诸如源极和漏极之类的金属线之间消除阻挡金属。 本发明是一种具有半导体层1，源电极2，漏电极3和透明导电膜4的薄膜晶体管基板，其中源电极2和漏电极3通过干式图案形成 并且包括包含0.1至1.5原子％的Si和/或Ge，0.1至3.0原子％的Ni和/或Co，以及0.1至0.5原子％的La和/或Nd的Al合金薄膜，并且薄膜 晶体管与半导体层1直接连接。

    THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE
    2.
    发明申请
    THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE 有权
    薄膜晶体管基板和显示器件

    公开(公告)号：US20100295053A1

    公开(公告)日：2010-11-25

    申请号：US12812913

    申请日：2009-01-15

    申请人： Mototaka Ochi ,  Nobuyuki Kawakami ,  Katsufumi Tomihisa ,  Hiroshi Goto

    发明人： Mototaka Ochi ,  Nobuyuki Kawakami ,  Katsufumi Tomihisa ,  Hiroshi Goto

    IPC分类号： H01L33/00 ,  H01L29/786

    CPC分类号： H01L29/458

    摘要： The present invention provides a thin film transistor substrate and a display device in which a decrease in the dry etching rate of a source electrode and drain electrode is not caused; no etching residues are generated; and a barrier metal can be eliminated between a semiconductor layer and metal wires such as the source and drain electrodes. The present invention is a thin film transistor substrate having a semiconductor layer 1, a source electrode 2, a drain electrode 3, and a transparent conductive film 4, in which the source electrode 2 and drain electrode 3 are formed by patterning by means of dry etching and comprises an Al alloy thin film comprising 0.1 to 1.5 atom % of Si and/or Ge, 0.1 to 3.0 atom % of Ni and/or Co, and 0.1 to 0.5 atom % of La and/or Nd, and the thin film transistor is directly connected with the semiconductor layer 1.

    摘要翻译： 本发明提供一种薄膜晶体管基板和显示装置，其中不会引起源电极和漏电极的干蚀刻速率的降低; 不产生蚀刻残留物; 并且可以在半导体层和诸如源极和漏极之类的金属线之间消除阻挡金属。 本发明是一种具有半导体层1，源电极2，漏电极3和透明导电膜4的薄膜晶体管基板，其中源电极2和漏电极3通过干式图案形成 并且包括包含0.1至1.5原子％的Si和/或Ge，0.1至3.0原子％的Ni和/或Co，以及0.1至0.5原子％的La和/或Nd的Al合金薄膜，并且薄膜 晶体管与半导体层1直接连接。

    Wiring structure, display apparatus, and semiconductor device
    9.
    发明授权
    Wiring structure, display apparatus, and semiconductor device 有权
    接线结构，显示装置和半导体器件

    公开(公告)号：US08598580B2

    公开(公告)日：2013-12-03

    申请号：US13639028

    申请日：2011-03-30

    申请人： Yasuaki Terao ,  Shinya Morita ,  Aya Miki ,  Katsufumi Tomihisa ,  Hiroshi Goto

    发明人： Yasuaki Terao ,  Shinya Morita ,  Aya Miki ,  Katsufumi Tomihisa ,  Hiroshi Goto

    IPC分类号： H01L29/16

    CPC分类号： H01L23/53238 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/3211 ,  H01L21/76867 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4958 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： Disclosed is a wiring structure that attains excellent low-contact resistance even if eliminating a barrier metal layer that normally is disposed between a Cu alloy wiring film and a semiconductor layer, and wiring structure with excellent adhesion. The wiring structure is provided with a semiconductor layer, and a Cu alloy layer, on a substrate in this order from the substrate side. A laminated structure is included between the semiconductor layer, and the Cu alloy layer. The laminated structure is composed of a (N, C, F, O) layer which contains at least one element selected from among a group composed of nitrogen, carbon, fluorine, and oxygen, and a Cu—Si diffusion layer which includes Cu and Si, in this order from the substrate side. At least one element selected from among the group composed of nitrogen, carbon, fluorine, and oxygen that composes the (N, C, F, O) layer is bonded to Si in the semiconductor layer. The Cu alloy layer is a laminated structure containing a Cu—X alloy layer (a first layer) and a second layer.

    摘要翻译： 公开了即使消除通常设置在Cu合金布线膜和半导体层之间的阻挡金属层以及具有优异的粘附性的布线结构，也可以获得优异的低接触电阻的布线结构。 布线结构在基板上依次从基板侧设置有半导体层和Cu合金层。 在半导体层和Cu合金层之间包含层叠结构。 层叠结构由含有选自氮，碳，氟和氧中的至少一种元素的（N，C，F，O）层构成，Cu-Si扩散层包含Cu和 Si，从衬底侧依次。 构成（N，C，F，O）层的由氮，碳，氟和氧构成的组中的至少一种元素与半导体层中的Si键合。 Cu合金层是含有Cu-X合金层（第一层）和第二层的层叠结构。

    WIRING STRUCTURE, DISPLAY APPARATUS, AND SEMICONDUCTOR DEVICE
    10.
    发明申请
    WIRING STRUCTURE, DISPLAY APPARATUS, AND SEMICONDUCTOR DEVICE 有权
    接线结构，显示设备和半导体器件

    公开(公告)号：US20130026470A1

    公开(公告)日：2013-01-31

    申请号：US13639028

    申请日：2011-03-30

    申请人： Yasuaki Terao ,  Shinya Morita ,  Aya Miki ,  Katsufumi Tomihisa ,  Hiroshi Goto

    发明人： Yasuaki Terao ,  Shinya Morita ,  Aya Miki ,  Katsufumi Tomihisa ,  Hiroshi Goto

    IPC分类号： H01L29/16

    CPC分类号： H01L23/53238 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/3211 ,  H01L21/76867 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4958 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： Disclosed is a wiring structure that attains excellent low-contact resistance even if eliminating a barrier metal layer that normally is disposed between a Cu alloy wiring film and a semiconductor layer, and wiring structure with excellent adhesion. The wiring structure is provided with a semiconductor layer, and a Cu alloy layer, on a substrate in this order from the substrate side. A laminated structure is included between the semiconductor layer, and the Cu alloy layer. The laminated structure is composed of a (N, C, F, O) layer which contains at least one element selected from among a group composed of nitrogen, carbon, fluorine, and oxygen, and a Cu—Si diffusion layer which includes Cu and Si, in this order from the substrate side. At least one element selected from among the group composed of nitrogen, carbon, fluorine, and oxygen that composes the (N, C, F, O) layer is bonded to Si in the semiconductor layer. The Cu alloy layer is a laminated structure containing a Cu—X alloy layer (a first layer) and a second layer.

    摘要翻译： 公开了即使消除通常设置在Cu合金布线膜和半导体层之间的阻挡金属层以及具有优异的粘附性的布线结构，也可以获得优异的低接触电阻的布线结构。 布线结构在基板上依次从基板侧设置有半导体层和Cu合金层。 在半导体层和Cu合金层之间包含层叠结构。 层叠结构由含有选自氮，碳，氟和氧中的至少一种元素的（N，C，F，O）层构成，Cu-Si扩散层包含Cu和 Si，从衬底侧依次。 构成（N，C，F，O）层的由氮，碳，氟和氧构成的组中的至少一种元素与半导体层中的Si键合。 Cu合金层是含有Cu-X合金层（第一层）和第二层的层叠结构。