公开(公告)号：US09859405B1

公开(公告)日：2018-01-02

申请号：US15610711

申请日：2017-06-01

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Shigeru Yoshida ,  Masahiro Shibata

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/417 ,  H01L29/40 ,  H01L29/66 ,  H01L29/12

CPC classification number: H01L29/737 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/12 ,  H01L29/20 ,  H01L29/401 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/66318 ,  H01L29/7371

Abstract: An HBT includes a semiconductor substrate having first and second principal surfaces opposite each other; and a collector layer, a base layer, and an emitter layer stacked in this order on the first principal surface side of the semiconductor substrate. The collector layer includes a first semiconductor layer with metal particles dispersed therein, the metal particles each formed by a plurality of metal atoms bonded with each other.

公开(公告)号：US11239187B2

公开(公告)日：2022-02-01

申请号：US16925006

申请日：2020-07-09

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tsutomu Kobori ,  Hiroshi Okabe ,  Shigeru Yoshida ,  Shingo Yanagihara ,  Yoshifumi Takahashi

IPC: H01L23/64 ,  H01L27/06 ,  H01L23/66 ,  H01L29/10 ,  H01L29/737 ,  H01L49/02

Abstract: A ground pad is disposed on a substrate. A plurality of transistors, each grounded at an emitter thereof, are in a first direction on a surface of the substrate. An input line connected to bases of the transistors is on the substrate. At least two shunt inductors are each connected at one end thereof to the input line and connected at the other end thereof to the ground pad. In the first direction, the two shunt inductors are on opposite sides of a center of a region where the transistors are arranged.

公开(公告)号：US10249620B2

公开(公告)日：2019-04-02

申请号：US15976682

申请日：2018-05-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Shigeru Yoshida ,  Kaoru Ideno

IPC: H03F1/02 ,  H01L23/66 ,  H01L27/06 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H03F3/195 ,  H03F3/213 ,  H01L27/082 ,  H01L29/205 ,  H01L29/417 ,  H01L29/737 ,  H01L21/8222 ,  H01L21/8252

Abstract: A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main surfaces opposing each other. The first bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a first emitter layer. The second bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer. The resistor layer is stacked on the second emitter layer in a direction normal to the first main surface.

公开(公告)号：US10374071B2

公开(公告)日：2019-08-06

申请号：US15598456

申请日：2017-05-18

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Shigeru Yoshida ,  Isao Obu

IPC: H01L29/66 ,  H01L29/73 ,  H01L29/737 ,  H01L29/02 ,  H01L31/109 ,  H01L29/36 ,  H01L31/072 ,  H01L29/08 ,  H01L29/15 ,  H01L21/02 ,  H01L21/331

Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, an emitter layer, and a semiconductor layer that are laminated in this order, wherein the emitter layer includes a first region having an upper surface on which the semiconductor layer is laminated, and a second region being adjacent to the first region and having an upper surface that is exposed, and the first and second regions of the emitter layer have higher doping concentrations in portions near the upper surfaces than in portions near an interface between the emitter layer and the base layer.

公开(公告)号：US10134842B2

公开(公告)日：2018-11-20

申请号：US15588859

申请日：2017-05-08

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Isao Obu ,  Shigeru Yoshida

IPC: H01L29/737 ,  H01L29/10 ,  H01L29/66 ,  H01L27/102 ,  H01L29/732 ,  H01L27/082 ,  H01L29/205 ,  H01L29/73 ,  H03F1/56 ,  H03F3/21 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08

Abstract: A high-performance HBT that is unlikely to decrease the process controllability and to increase the manufacturing cost is implemented. A heterojunction bipolar transistor includes an emitter layer, a base layer, and a collector layer on a GaAs substrate. The emitter layer is formed of InGaP. The base layer is formed of GaAsPBi having a composition that substantially lattice-matches GaAs.

公开(公告)号：US10355114B2

公开(公告)日：2019-07-16

申请号：US15820897

申请日：2017-11-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Shigeru Yoshida ,  Masahiro Shibata

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/12 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/20

Abstract: An HBT includes a semiconductor substrate having first and second principal surfaces opposite each other; and a collector layer, a base layer, and an emitter layer stacked in this order on the first principal surface side of the semiconductor substrate. The collector layer includes a first semiconductor layer with metal particles dispersed therein, the metal particles each formed by a plurality of metal atoms bonded with each other.

公开(公告)号：US09997516B2

公开(公告)日：2018-06-12

申请号：US15446785

申请日：2017-03-01

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Isao Obu ,  Shigeru Yoshida ,  Kaoru Ideno

IPC: H01L27/082 ,  H01L29/737 ,  H03F3/195 ,  H03F3/213 ,  H01L23/66 ,  H03F1/02 ,  H01L29/04

CPC classification number: H01L27/082 ,  H01L23/66 ,  H01L29/045 ,  H01L29/0692 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/737 ,  H01L29/7371 ,  H03F1/0238 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451

Abstract: A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main surfaces opposing each other. The first bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a first emitter layer. The second bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer. The resistor layer is stacked on the second emitter layer in a direction normal to the first main surface.